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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-10-12 19:07:15 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-13 23:59:15 +0000 |
| commit | a5f11ebdd70eb4d05a309c02eebebd342897acea (patch) | |
| tree | 922dfe5adade8737582a8c69c87b9487de28ed45 /src/mainboard/google/kahlee/variants/nuwani/devicetree.cb | |
| parent | b68e22409d8e22e097193bd26cb31213c7030db7 (diff) | |
| download | coreboot-a5f11ebdd70eb4d05a309c02eebebd342897acea.tar.gz coreboot-a5f11ebdd70eb4d05a309c02eebebd342897acea.tar.bz2 coreboot-a5f11ebdd70eb4d05a309c02eebebd342897acea.zip | |
mb/amd,google/*/devicetree: drop CPU cluster device for Stoneyridge
Since commit 60e9114c6210 ("include/device: ensure valid link/bus is
passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the
CPU cluster device. Since the CPU cluster device is already present in
the Stoneyridge chipset devicetree, drop the whole CPU cluster part from
the mainboard's devicetrees.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/variants/nuwani/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/nuwani/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index db77bd5c78e3..ae2379cb1e93 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -47,9 +47,6 @@ chip soc/amd/stoneyridge register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ GPIO_I2C2_SCL | GPIO_I2C3_SCL" - device cpu_cluster 0 on - device lapic 10 on end - end device domain 0 on device pci 0.0 on end # Root Complex device pci 0.2 off end # IOMMU (Disabled for performance and battery) |