mb/google/hatch: split up hatch and puff baseboards

The hatch and puff baseboards have diverged enough to where it makes
more sense to split them into separate boards. Copy the mb/google/hatch
directory into a new dir 'puff' and strip out all boards and items
related to the hatch baseboard. Remove all puff-related items from the
original hatch directory. Clean up and alphabetize Kconfig selections.

Test: build and boot akemi hatch variant and wyvern puff variant.

Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 1310 insertions, 0 deletions

diff --git a/src/mainboard/google/puff/variants/baseboard/Makefile.inc b/src/mainboard/google/puff/variants/baseboard/Makefile.inc
new file mode 100644
index 000000000000..e4641b977e28
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/Makefile.inc
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += mainboard.c
+
+verstage-y += gpio.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
new file mode 100644
index 000000000000..976d82970c8f
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
@@ -0,0 +1,355 @@
+chip soc/intel/cannonlake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# DW1 is used by:
+	#   - GPP_C1  - PCIE_14_WLAN_WAKE_ODL
+	#   - GPP_C21 - H1_PCH_INT_ODL
+	register "gpe0_dw0" = "PMC_GPP_A"
+	register "gpe0_dw1" = "PMC_GPP_C"
+	register "gpe0_dw2" = "PMC_GPP_D"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	# FSP configuration
+	register "SkipExtGfxScan" = "1"
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[1]" = "1"
+	# Configure devslp pad reset to PLT_RST
+	register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset"
+	register "satapwroptimize" = "1"
+	# Enable System Agent dynamic frequency
+	register "SaGv" = "SaGv_Enabled"
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+	# Enable DPTF
+	register "dptf_enable" = "1"
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 64,
+	}"
+	register "Device4Enable" = "1"
+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+	register "tcc_offset" = "10"	# TCC of 90C
+	# Unlock GPIO pads
+	register "PchUnlockGpioPads" = "1"
+	# SD card WP pin configuration
+	register "ScsSdCardWpPinEnabled" = "0"
+
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
+	register "common_soc_config.pch_thermal_trip" = "77"
+
+	# Select CPU PL2/PL4 config
+	register "cpu_pl2_4_cfg" = "baseline"
+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-------+-------+-------+-------+
+	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
+	#+----------------+-------+-------+-------+-------+
+	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
+	#| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
+	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
+	#| Psi3Enable     | 1     | 1     | 1     | 1     |
+	#| Psi4Enable     | 1     | 1     | 1     | 1     |
+	#| ImonSlope      | 0     | 0     | 0     | 0     |
+	#| ImonOffset     | 0     | 0     | 0     | 0     |
+	#| IccMax         | 6A    | 70A   | 31A   | 31A   |
+	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+	#| AcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
+	#| DcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
+	#+----------------+-------+-------+-------+-------+
+	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 1030,
+		.dc_loadline = 1030,
+	}"
+
+	register "domain_vr_config[VR_IA_CORE]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 180,
+		.dc_loadline = 180,
+	}"
+
+	register "domain_vr_config[VR_GT_UNSLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 310,
+		.dc_loadline = 310,
+	}"
+
+	register "domain_vr_config[VR_GT_SLICED]" = "{
+		.vr_config_enable = 1,
+		.psi1threshold = VR_CFG_AMP(20),
+		.psi2threshold = VR_CFG_AMP(5),
+		.psi3threshold = VR_CFG_AMP(1),
+		.psi3enable = 1,
+		.psi4enable = 1,
+		.imon_slope = 0x0,
+		.imon_offset = 0x0,
+		.icc_max = 0,
+		.voltage_limit = 1520,
+		.ac_loadline = 310,
+		.dc_loadline = 310,
+	}"
+
+	register "PchPmSlpS3MinAssert" = "2"  # 50ms
+	register "PchPmSlpS4MinAssert" = "1"  # 1s
+	register "PchPmSlpSusMinAssert" = "1" # 500ms
+	register "PchPmSlpAMinAssert" = "3"   # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#	- GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#	- GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#	- PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#	- PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
+	# Enable Audio DSP oscillator qualification for S0ix
+	register "cppmvric2_adsposcdis" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1
+	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)"	# Type-A Port 0
+	register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)"	# Type-A Port 1
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
+	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port 0
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port 1
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
+
+	# Enable Root port 9(x4) for NVMe.
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	# RP 9 uses CLK SRC 1
+	register "PcieClkSrcUsage[1]" = "8"
+	# ClkReq-to-ClkSrc mapping for CLK SRC 1
+	register "PcieClkSrcClkReq[1]" = "1"
+
+	# PCIe port 14 for M.2 E-key WLAN
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	# RP 14 uses CLK SRC 3
+	register "PcieClkSrcUsage[3]" = "13"
+	register "PcieClkSrcClkReq[3]" = "3"
+
+	#Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override)
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkSsp0" = "1"
+	register "PchHdaAudioLinkSsp1" = "1"
+	register "PchHdaAudioLinkDmic0" = "1"
+	register "PchHdaAudioLinkDmic1" = "0"
+
+	# GPIO PM programming
+	register "gpio_override_pm" = "1"
+
+	# GPIO community PM configuration
+	# Disable dynamic clock gating; with bits 0-5 set in these registers,
+	# some short interrupt pulses were missed (esp. cr50 irq)
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 off end # SA Thermal device
+		device pci 05.0 off end # SA IPU
+		device pci 12.0 on end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device usb 2.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port 1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device usb 2.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-A Port""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device usb 2.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-A Port 1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device usb 2.3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
+						device usb 2.9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device usb 3.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port 1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device usb 3.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-A Port""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device usb 3.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-A Port 1""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "group" = "ACPI_PLD_GROUP(2, 2)"
+						device usb 3.3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.4 on end
+					end
+				end
+			end
+		end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.3 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end # CNVi wifi
+		device pci 14.5 on  end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 on  end # I2C #2
+		device pci 15.3 on  end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 on  end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 off end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1c.0 off end # PCI Express Port 1 (USB)
+		device pci 1c.1 off end # PCI Express Port 2 (USB)
+		device pci 1c.2 off end # PCI Express Port 3 (USB)
+		device pci 1c.3 off end # PCI Express Port 4 (USB)
+		device pci 1c.4 off end # PCI Express Port 5 (USB)
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on	# PCI Express Port 9 (X4 NVME)
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express port 13
+		device pci 1d.5 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_01"
+				device pci 00.0 on  end
+			end
+			register "PcieRpSlotImplemented[13]" = "1"
+		end # PCI Express Port 14 (x4)
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #0
+		device pci 1e.3 on end # GSPI #1
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # eSPI Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 hidden end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/google/puff/variants/baseboard/gpio.c b/src/mainboard/google/puff/variants/baseboard/gpio.c
new file mode 100644
index 000000000000..eab831aabf75
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/gpio.c
@@ -0,0 +1,435 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static const struct pad_config gpio_table[] = {
+	/* A0  : GPP_A0 ==> NC */
+	PAD_NC(GPP_A0, NONE),
+	/* A1  : ESPI_IO0 */
+	/* A2  : ESPI_IO1 */
+	/* A3  : ESPI_IO2 */
+	/* A4  : ESPI_IO3 */
+	/* A5  : ESPI_CS# */
+	/* A6  : GPP_A6 ==> NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A7  : PP3300_SOC_A */
+	PAD_NC(GPP_A7, NONE),
+	/* A8  : GPP_A8 ==> NC */
+	PAD_NC(GPP_A8, NONE),
+	/* A9  : ESPI_CLK */
+	/* A10  : GPP_A10 ==> NC */
+	PAD_NC(GPP_A10, NONE),
+	/* A11  : GPP_A11 ==> NC */
+	PAD_NC(GPP_A11, NONE),
+	/* A12  : GPP_A12 ==> NC */
+	PAD_NC(GPP_A12, NONE),
+	/* A13 : SUSWARN_L */
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+	/* A14 : ESPI_RST_L */
+	/* A15 : SUSACK_L */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : SD_1P8_SEL => NC */
+	PAD_NC(GPP_A16, NONE),
+	/* A17 : EN_PP3300_SD_DX */
+	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+	/* A18 : EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A18, 1, DEEP),
+	/* A19 : WWAN_RADIO_DISABLE_1V8_ODL */
+	PAD_CFG_GPO(GPP_A19, 1, DEEP),
+	/* A20 : WLAN_INT_L */
+	PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
+	/* A21 : TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT),
+	/* A22 : FPMCU_PCH_BOOT0 */
+	PAD_CFG_GPO(GPP_A22, 0, DEEP),
+	/* A23 : FPMCU_PCH_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
+
+	/* B0  : CORE_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : CORE_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2  : GPP_B2 ==> NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B3  : GPP_B3 ==> NC */
+	PAD_NC(GPP_B3, NONE),
+	/* B4  : GPP_B4 ==> NC */
+	PAD_NC(GPP_B4, NONE),
+	/* B5  : GPP_B5 ==> NC */
+	PAD_NC(GPP_B5, NONE),
+	/* B6  : SRCCLKREQ1 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	/* B7  : GPP_B7 ==> NC */
+	PAD_NC(GPP_B7, NONE),
+	/* B8  : PCIE_14_WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+	/* B9  : GPP_B9 ==> NC */
+	PAD_NC(GPP_B9, NONE),
+	/* B10 : GPP_B10 ==> NC */
+	PAD_NC(GPP_B10, NONE),
+	/* B11 : EXT_PWR_GATE_L */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* B12 : SLP_S0_L */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLT_RST_L */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14 : GPP_B14_STRAP */
+	PAD_NC(GPP_B14, NONE),
+	/* B15 : H1_SLAVE_SPI_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B16 : H1_SLAVE_SPI_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	/* B17 : H1_SLAVE_SPI_MISO_R */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+	/* B18 : H1_SLAVE_SPI_MOSI_R */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : PCH_SPI_FPMCU_CLK_R */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : PCH_SPI_FPMCU_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+	/* B22 : PCH_SPI_FPMCU_MOSI */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+	/* B23 : GPP_B23_STRAP */
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0  : GPP_C0 => NC */
+	PAD_NC(GPP_C0, NONE),
+	/* C1  : PCIE_14_WLAN_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE),
+	/* C2  : GPP_C2 => NC */
+	PAD_NC(GPP_C2, NONE),
+	/* C3  : WLAN_OFF_L */
+	PAD_CFG_GPO(GPP_C3, 1, DEEP),
+	/* C4  : TOUCHSCREEN_DIS_L */
+	PAD_CFG_GPO(GPP_C4, 1, DEEP),
+	/* C5  : GPP_C5 => NC */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : PEN_PDCT_OD_L */
+	PAD_NC(GPP_C6, NONE),
+	/* C7  : PEN_IRQ_OD_L */
+	PAD_NC(GPP_C7, NONE),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+	/* C10 : GPP_10 ==> GPP_C10_TP */
+	PAD_NC(GPP_C10, NONE),
+	/* C11 : GPP_11 ==> EN_FP_RAILS */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
+	/* C12 : GPP_C12 ==> NC */
+	PAD_NC(GPP_C12, NONE),
+	/* C13 : EC_PCH_INT_L */
+	PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
+	/* C14 : BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_C14, 1, DEEP),
+	/* C15 : NC */
+	PAD_NC(GPP_C15, NONE),
+	/* C16 : PCH_I2C_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* C17 : PCH_I2C_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* C18 : PCH_I2C_TOUCHSCREEN_SDA */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* C19 : PCH_I2C_TOUCHSCREEN_SCL */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* C20 : PCH_WP_OD */
+	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+	/* C21 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+	/* C22 : EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+	/* C23 : WLAN_PE_RST# */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+	/* D0  : TP31 */
+	PAD_NC(GPP_D0, NONE),
+	/* D1  : TP16 */
+	PAD_NC(GPP_D1, NONE),
+	/* D2  : TP26 */
+	PAD_NC(GPP_D2, NONE),
+	/* D3  : TP27 */
+	PAD_NC(GPP_D3, NONE),
+	/* D4  : TP40 */
+	PAD_NC(GPP_D4, NONE),
+	/* D5  : WWAN_CONFIG_0 */
+	PAD_NC(GPP_D5, NONE),
+	/* D6  : WWAN_CONFIG_1 */
+	PAD_NC(GPP_D6, NONE),
+	/* D7  : WWAN_CONFIG_2 */
+	PAD_NC(GPP_D7, NONE),
+	/* D8  : WWAN_CONFIG_3 */
+	PAD_NC(GPP_D8, NONE),
+	/* D9  : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	/* D10 : GPP_D10 ==> NC */
+	PAD_NC(GPP_D10, NONE),
+	/* D11 : GPP_D11 ==> NC */
+	PAD_NC(GPP_D11, NONE),
+	/* D12 : GPP_D12 */
+	PAD_NC(GPP_D12, NONE),
+	/* D13 : ISH_UART_RX */
+	PAD_NC(GPP_D13, NONE),
+	/* D14 : ISH_UART_TX */
+	PAD_NC(GPP_D14, NONE),
+	/* D15 : TOUCHSCREEN_RST_L */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	/* D16 : USI_INT */
+	PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE),
+	/* D17 : PCH_HP_SDW_CLK */
+	PAD_NC(GPP_D17, NONE),
+	/* D18 : PCH_HP_SDW_DAT */
+	PAD_NC(GPP_D18, NONE),
+	/* D19 : DMIC_CLK_0_SNDW4_CLK */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	/* D20 : DMIC_DATA_0_SNDW4_DATA */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	/* D21 : GPP_D21 ==> NC */
+	PAD_NC(GPP_D21, NONE),
+	/* D22 : GPP_D22 ==> NC */
+	PAD_NC(GPP_D22, NONE),
+	/* D23 : SPP_MCLK */
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+
+	/* E0  : GPP_E0 ==> NC */
+	PAD_NC(GPP_E0, NONE),
+	/* E1  : M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+	/* E2  : GPP_E2 ==> NC */
+	PAD_NC(GPP_E2, NONE),
+	/* E3  : GPP_E3 ==> NC */
+	PAD_NC(GPP_E3, NONE),
+	/* E4  : M2_SSD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	/* E5  : SATA_DEVSLP1 */
+	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+	/* E6  : M2_SSD_RST_L */
+	PAD_NC(GPP_E6, NONE),
+	/* E7  : GPP_E7 ==> NC */
+	PAD_NC(GPP_E7, NONE),
+	/* E8  : GPP_E8 ==> NC */
+	PAD_NC(GPP_E8, NONE),
+	/* E9  : GPP_E9 ==> NC */
+	PAD_NC(GPP_E9, NONE),
+	/* E10 : GPP_E10 ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* E11 : USB_C_OC_OD USB_OC2 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* E12 : USB_A_OC_OD USB_OC3 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* E13 : USB_C0_DP_HPD */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* E14 : DDI2_HPD_ODL */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : DDPD_HPD2 =>  NC */
+	PAD_NC(GPP_E15, NONE),
+	/* E16 : DDPE_HPD2 => NC */
+	PAD_NC(GPP_E16, NONE),
+	/* E17 : EDP_HPD */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	/* E18 : DDPB_CTRLCLK => NC */
+	PAD_NC(GPP_E18, NONE),
+	/* E19 : GPP_E19_STRAP */
+	PAD_CFG_GPI(GPP_E19, NONE, DEEP),
+	/* E20 : DDPC_CTRLCLK => NC */
+	PAD_NC(GPP_E20, NONE),
+	/* E21 : GPP_E21_STRAP */
+	PAD_CFG_GPI(GPP_E21, NONE, DEEP),
+	/* E22 : DDPD_CTRLCLK => NC */
+	PAD_NC(GPP_E22, NONE),
+	/* E23 : GPP_E23_STRAP */
+	PAD_NC(GPP_E23, NONE),
+
+	/* F0  : GPIO_WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : WWAN_RESET_1V8_ODL */
+	PAD_CFG_GPO(GPP_F1, 1, DEEP),
+	/* F2  : MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
+	/* F3  : GPP_F3 ==> NC */
+	PAD_NC(GPP_F3, NONE),
+	/* F4  : CNV_BRI_DT */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+	/* F6  : CNV_RGI_DT */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F7  : CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+	/* F8  : UART_WWANTX_WLANRX_COEX1 */
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+	/* F9  : UART_WWANRX_WLANTX_COEX2 */
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+	/* F10 : GPP_F10 ==> NC */
+	PAD_NC(GPP_F10, NONE),
+	/* F11 : PCH_MEM_STRAP2 */
+	PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
+	/* F12 : GPP_F12 ==> NC */
+	PAD_NC(GPP_F12, NONE),
+	/* F13 : GPP_F13 ==> NC */
+	PAD_NC(GPP_F13, NONE),
+	/* F14 : GPP_F14 ==> NC */
+	PAD_NC(GPP_F14, NONE),
+	/* F15 : GPP_F15 ==> NC */
+	PAD_NC(GPP_F15, NONE),
+	/* F16 : GPP_F16 ==> NC */
+	PAD_NC(GPP_F16, NONE),
+	/* F17 : GPP_F17 ==> NC */
+	PAD_NC(GPP_F17, NONE),
+	/* F18 : GPP_F18 ==> NC */
+	PAD_NC(GPP_F18, NONE),
+	/* F19 : GPP_F19 ==> NC */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : PCH_MEM_STRAP0 */
+	PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
+	/* F21 : PCH_MEM_STRAP1 */
+	PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
+	/* F22 : PCH_MEM_STRAP3 */
+	PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
+	/* F23 : GPP_F23 ==> NC */
+	PAD_NC(GPP_F23, NONE),
+
+	/* G0  : SD_CMD */
+	PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
+	/* G1  : SD_DATA0 */
+	PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
+	/* G2  : SD_DATA1 */
+	PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
+	/* G3  : SD_DATA2 */
+	PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
+	/* G4  : SD_DATA3 */
+	PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
+	/* G5  : SD_CD# */
+	PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
+	/* G6  : SD_CLK */
+	PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+	/* G7  : SD_WP
+	 * As per schematics SD host controller SD_WP pin is not connected to
+	 * uSD card connector. In order to overcome gpio default state, ensures
+	 * to configure gpio pin as NF1 with internal 20K pull down.
+	 */
+	PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
+	/*
+	 * H0  : HP_INT_L
+	 */
+	PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH),
+	/* H1  : CNV_RF_RESET_L */
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
+	/* H2  : CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+	/* H3 : GPP_H3 ==> NC */
+	PAD_NC(GPP_H3, NONE),
+	/* H4  : PCH_I2C_PEN_SDA */
+	PAD_NC(GPP_H4, NONE),
+	/* H5  : PCH_I2C_PEN_SCL */
+	PAD_NC(GPP_H5, NONE),
+	/* H6  : PCH_I2C_SAR0_MST_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : PCH_I2C_SAR0_MST_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8  : PCH_I2C_M2_AUDIO_SAR1_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* H9  : PCH_I2C_M2_AUDIO_SAR1_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H10 : PCH_I2C_TRACKPAD_SDA */
+	PAD_NC(GPP_H10, NONE),
+	/* H11 : PCH_I2C_TRACKPAD_SCL */
+	PAD_NC(GPP_H11, NONE),
+	/* H12 : GPP_H12 ==> NC */
+	PAD_NC(GPP_H12, NONE),
+	/* H13 : GPP_H13 ==> NC */
+	PAD_NC(GPP_H13, NONE),
+	/* H14 : GPP_H14 ==> NC */
+	PAD_NC(GPP_H14, NONE),
+	/* H15 : GPP_H15 ==> NC */
+	PAD_NC(GPP_H15, NONE),
+	/* H16 : GPP_H16 ==> NC */
+	PAD_NC(GPP_H16, NONE),
+	/* H17 : TP1 */
+	PAD_NC(GPP_H17, NONE),
+	/* H18 : CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : GPP_H19 ==> NC */
+	PAD_NC(GPP_H19, NONE),
+	/* H20 : TP41 */
+	PAD_NC(GPP_H20, NONE),
+	/* H21 : XTAL_FREQ_SEL */
+	PAD_NC(GPP_H21, NONE),
+	/* H22 : GPP_H22 ==> NC */
+	PAD_NC(GPP_H22, NONE),
+	/* H23 : GPP_H23_STRAP */
+	PAD_NC(GPP_H23, NONE),
+
+	/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+
+	/* SD card detect VGPIO */
+	PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP),
+
+	/* CNV_WCEN  : Disable Wireless Charging */
+	PAD_CFG_GPO(CNV_WCEN, 0, DEEP),
+};
+
+const struct pad_config *base_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+/*
+ * Default GPIO settings before entering non-S5 sleep states.
+ * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
+ * This guarantees that A12's native3 function is disabled.
+ * See https://review.coreboot.org/c/coreboot/+/32111 .
+ */
+static const struct pad_config default_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
+};
+
+/*
+ * GPIO settings before entering S5, which are same as
+ * default_sleep_gpio_table but also,
+ * turn off EN_PP3300_WWAN and FPMCU.
+ */
+static const struct pad_config s5_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
+	PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
+};
+
+const struct pad_config *__weak variant_sleep_gpio_table(
+	u8 slp_typ, size_t *num)
+{
+	if (slp_typ == ACPI_S5) {
+		*num = ARRAY_SIZE(s5_sleep_gpio_table);
+		return s5_sleep_gpio_table;
+	}
+	*num = ARRAY_SIZE(default_sleep_gpio_table);
+	return default_sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);
+
+/* Weak implementation of overrides */
+const struct pad_config *__weak override_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+/* Weak implementation of early gpio */
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl
new file mode 100644
index 000000000000..ef9b5694fa89
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define DPTF_CPU_PASSIVE	95
+#define DPTF_CPU_CRITICAL	105
+#define DPTF_CPU_ACTIVE_AC0	87
+#define DPTF_CPU_ACTIVE_AC1	85
+#define DPTF_CPU_ACTIVE_AC2	83
+#define DPTF_CPU_ACTIVE_AC3	80
+#define DPTF_CPU_ACTIVE_AC4	75
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
+#define DPTF_TSR0_PASSIVE	65
+#define DPTF_TSR0_CRITICAL	75
+#define DPTF_TSR0_ACTIVE_AC0	50
+#define DPTF_TSR0_ACTIVE_AC1	47
+#define DPTF_TSR0_ACTIVE_AC2	45
+#define DPTF_TSR0_ACTIVE_AC3	42
+#define DPTF_TSR0_ACTIVE_AC4	39
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Thermal Sensor 2"
+#define DPTF_TSR1_PASSIVE	65
+#define DPTF_TSR1_CRITICAL	75
+#define DPTF_TSR1_ACTIVE_AC0	50
+#define DPTF_TSR1_ACTIVE_AC1	47
+#define DPTF_TSR1_ACTIVE_AC2	45
+#define DPTF_TSR1_ACTIVE_AC3	42
+#define DPTF_TSR1_ACTIVE_AC4	39
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+})
+
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {60,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {50,		0xFFFFFFFF,	3838,	90,	900},
+	Package () {40,		0xFFFFFFFF,	2904,	55,	550},
+	Package () {30,		0xFFFFFFFF,	2337,	30,	300},
+	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
+	Package () {10,		0xFFFFFFFF,	800,	10,	100},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	}
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on Ambient (TSR0) */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+
+	/* Charger Throttle Effect on Charger (TSR1) */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		3000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		15000,	/* PowerLimitMinimum */
+		64000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 000000000000..4760adc31610
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(MAINBOARD_EC_S3_WAKE_EVENTS | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 000000000000..6c549789960e
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+#define GPIO_EC_IN_RW	        GPP_C22
+
+#define GPIO_PCH_WP	        GPP_C20
+
+/* EC wake pin is routed to GPD2/LAN_WAKE# on PCH */
+#define GPE_EC_WAKE		GPE0_LAN_WAK
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+
+/* EC sync irq is GPP_C13_IRQ */
+#define EC_SYNC_IRQ             GPP_C13_IRQ
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 000000000000..125f7388a1cd
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/gpio.h>
+#include <stdint.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.  The "base" GPIOs live in the "baseboard" variant, and
+ * the overrides live with the specific board (kohaku, kled, etc.).
+*/
+const struct pad_config *base_gpio_table(size_t *num);
+const struct pad_config *override_gpio_table(size_t *num);
+
+/* Return board specific memory configuration */
+void variant_memory_params(struct cnl_mb_cfg *bcfg);
+
+/* Return memory SKU for the variant */
+int variant_memory_sku(void);
+
+/* Return variant specific gpio pads to be configured during sleep */
+const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num);
+
+/* Return GPIO pads that need to be configured before ramstage */
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+/* Modify devictree settings during ramstage. */
+void variant_devtree_update(void);
+
+/* Perform variant specific initialization early on in ramstage. */
+void variant_ramstage_init(void);
+
+/* Perform variant specific mainboard initialization */
+void variant_mainboard_enable(struct device *dev);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/puff/variants/baseboard/include/puff/ec.h b/src/mainboard/google/puff/variants/baseboard/include/puff/ec.h
new file mode 100644
index 000000000000..986cf61c05fa
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/include/puff/ec.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS 0
+
+/* EC can wake from S5 with power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with power button */
+#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+	(MAINBOARD_EC_S3_WAKE_EVENTS | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable cros_ec_keyb device */
+#define EC_ENABLE_MKBP_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/*
+ * Defines EC wake pin route.
+ * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
+ * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
+ */
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/google/puff/variants/baseboard/mainboard.c b/src/mainboard/google/puff/variants/baseboard/mainboard.c
new file mode 100644
index 000000000000..e0c344064c42
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/mainboard.c
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootmode.h>
+#include <chip.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <intelblocks/power_limit.h>
+#include <soc/pci_devs.h>
+#include <timer.h>
+
+#define GPIO_HDMI_HPD		GPP_E13
+#define GPIO_DP_HPD		GPP_E14
+
+/* TODO: This can be moved to common directory */
+static void wait_for_hpd(gpio_t gpio, long timeout)
+{
+	struct stopwatch sw;
+
+	printk(BIOS_INFO, "Waiting for HPD\n");
+	stopwatch_init_msecs_expire(&sw, timeout);
+	while (!gpio_get(gpio)) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_WARNING,
+			       "HPD not ready after %ldms. Abort.\n", timeout);
+			return;
+		}
+		mdelay(200);
+	}
+	printk(BIOS_INFO, "HPD ready after %lld ms\n",
+	       stopwatch_duration_msecs(&sw));
+}
+
+/*
+ * For type-C chargers, set PL2 to 97% of max power to account for
+ * cable loss and FET Rdson loss in the path from the source.
+ */
+#define SET_PSYSPL2(w)               (97 * (w) / 100)
+#define PUFF_U22_PL2                 (35)
+#define PUFF_U62_U42_PL2             (51)
+#define PUFF_CELERON_PENTIUM_PSYSPL2 (65)
+#define PUFF_CORE_CPU_PSYSPL2        (90)
+#define PUFF_MAX_TIME_WINDOW         6
+#define PUFF_MIN_DUTYCYCLE           4
+
+/*
+ * mainboard_set_power_limits
+ *
+ * Set Pl2 and SysPl2 values based on detected charger.
+ * Values are defined below but we use U22 value for all SKUs for now.
+ * definitions:
+ * x = no value entered. Use default value in parenthesis.
+ *     will set 0 to anything that shouldn't be set.
+ * n = max value of power adapter.
+ * +-------------+-----+---------+-----------+-------+
+ * | sku_id      | PL2 | PsysPL2 |  PsysPL3  |  PL4  |
+ * +-------------+-----+---------+-----------+-------+
+ * | i7 U42      |  51 |   90    | x(.85PL4) | x(82) |
+ * | i3 U22      |  35 |   65    | x(.85PL4) | x(51) |
+ * +-------------+-----+---------+-----------+-------+
+ * For USB C charger:
+ * +-------------+-----------------+---------+---------+-------+
+ * | Max Power(W)|       PL2       | PsysPL2 | PsysPL3 |  PL4  |
+ * +-------------+-----+-----------+---------+---------+-------+
+ * | n           | min(0.97n, PL2) |  0.97n  |  0.97n  | 0.97n |
+ * +-------------+-----+-----------+---------+---------+-------+
+ */
+
+/*
+ * Psys_pmax considerations
+ *
+ * Given the hardware design in puff, the serial shunt resistor is 0.01ohm.
+ * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A
+ * instead of real system power. The equation is shown below:
+ * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k)
+ * Hence, Iinput (Amps) = 9.6A
+ * Since there is no voltage information from PSYS, different voltage input
+ * would map to different Psys_pmax settings:
+ * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W
+ * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W
+ * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W
+ */
+#define PSYS_IMAX    9600
+#define BJ_VOLTS_MV  19000
+
+static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
+{
+	enum usb_chg_type type;
+	u32 watts;
+	u16 volts_mv, current_ma;
+	u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value
+	u32 pl2 = PUFF_U22_PL2; // default PL2 for U22
+	int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+	u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
+
+	/* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
+	conf->tdp_psyspl3 = 0;
+	conf->tdp_pl4 = 0;
+
+	if (rv == 0 && type == USB_CHG_TYPE_PD) {
+		/* Detected USB-PD.  Base on max value of adapter */
+		watts = ((u32)current_ma * volts_mv) / 1000000;
+		/* set psyspl2 to 90% of adapter rating */
+		psyspl2 = SET_PSYSPL2(watts);
+
+		/* Limit PL2 if the adapter is with lower capability */
+		if (mch_id == PCI_DID_INTEL_CML_ULT ||
+			mch_id == PCI_DID_INTEL_CML_ULT_6_2)
+			pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2;
+		else
+			pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2;
+
+		conf->tdp_psyspl3 = psyspl2;
+		/* set max possible time window */
+		conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
+		/* set minimum duty cycle */
+		conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
+		/* No data about an arbitrary Type-C adapter, set pl4 conservatively. */
+		conf->tdp_pl4 = psyspl2;
+	} else {
+		/*
+		 * Input type is barrel jack, from the SKU matrix:
+		 * 1. i3/i5/i7 SKUs use 90W BJ
+		 * 2. Celeron and Pentium use 65W BJ (default)
+		 */
+		volts_mv = BJ_VOLTS_MV;
+		/* Use IGD ID to check if CPU is Core SKUs */
+		if (igd_id != PCI_DID_INTEL_CML_GT1_ULT_1 &&
+			igd_id != PCI_DID_INTEL_CML_GT2_ULT_5) {
+			psyspl2 = PUFF_CORE_CPU_PSYSPL2;
+			if (mch_id == PCI_DID_INTEL_CML_ULT ||
+				mch_id == PCI_DID_INTEL_CML_ULT_6_2)
+				pl2 = PUFF_U62_U42_PL2;
+		}
+	}
+	/* voltage unit is milliVolts and current is in milliAmps */
+	conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
+
+	conf->tdp_pl2_override = pl2;
+	conf->tdp_psyspl2 = psyspl2;
+}
+
+void variant_ramstage_init(void)
+{
+	static const long display_timeout_ms = 3000;
+	struct soc_power_limits_config *soc_config;
+	config_t *conf = config_of_soc();
+
+	/* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
+	gpio_input(GPIO_HDMI_HPD);
+	gpio_input(GPIO_DP_HPD);
+	if (display_init_required()
+		&& !gpio_get(GPIO_HDMI_HPD)
+		&& !gpio_get(GPIO_DP_HPD)) {
+		/* This has to be done before FSP-S runs. */
+		if (google_chromeec_wait_for_displayport(display_timeout_ms))
+			wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
+	}
+	/* Psys_pmax needs to be setup before FSP-S */
+	soc_config = &conf->power_limits_config;
+	mainboard_set_power_limits(soc_config);
+}
diff --git a/src/mainboard/google/puff/variants/baseboard/memory.c b/src/mainboard/google/puff/variants/baseboard/memory.c
new file mode 100644
index 000000000000..5df73333a690
--- /dev/null
+++ b/src/mainboard/google/puff/variants/baseboard/memory.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <soc/cnl_memcfg_init.h>
+#include <string.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg = {
+	/* Baseboard uses 121, 81 and 100 rcomp resistors */
+	.rcomp_resistor = {121, 81, 100},
+
+	/* Baseboard Rcomp target values */
+	.rcomp_targets = {100, 40, 20, 20, 26},
+
+	/* Set CaVref config to 2 */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+};
+
+void __weak variant_memory_params(struct cnl_mb_cfg *bcfg)
+{
+	memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
+}