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| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-28 13:05:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-04 11:48:19 +0000 |
| commit | af4bd5633debc8838b563c3fadd96e2b4b060ab5 (patch) | |
| tree | 6867d466f6e3b7ca8e6077979a404caf7609a747 /src/mainboard/google/stout | |
| parent | 0b9d186e3dc7c209d0fc26b61db3cd98550b71bd (diff) | |
| download | coreboot-af4bd5633debc8838b563c3fadd96e2b4b060ab5.tar.gz coreboot-af4bd5633debc8838b563c3fadd96e2b4b060ab5.tar.bz2 coreboot-af4bd5633debc8838b563c3fadd96e2b4b060ab5.zip | |
sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/stout')
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ad700cee2927..b38adaf14809 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x0001C1611" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 |