summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
diff options
context:
space:
mode:
authorFelix Singer <felixsinger@posteo.net>2021-12-05 02:40:26 +0100
committerFelix Singer <felixsinger@posteo.net>2021-12-09 21:52:13 +0000
commit715b787fd3d1a0e714da795ea3d3eaf28ca49577 (patch)
tree36bddb19913ef007da7ba6d4aa29758e21ca189f /src/mainboard/google/volteer/variants/baseboard/devicetree.cb
parent2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8 (diff)
downloadcoreboot-715b787fd3d1a0e714da795ea3d3eaf28ca49577.tar.gz
coreboot-715b787fd3d1a0e714da795ea3d3eaf28ca49577.tar.bz2
coreboot-715b787fd3d1a0e714da795ea3d3eaf28ca49577.zip
soc/intel/tigerlake: Hook up SMBus device to devicetree
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index b4c4f6a41fe8..eee29ef2cee0 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -92,7 +92,6 @@ chip soc/intel/tigerlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "SmbusEnable" = "0"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1