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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-25 21:07:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-27 16:43:15 +0000 |
| commit | 0fec867e32a2df821e5a3569496b1dda7a2b1d5f (patch) | |
| tree | 12afe2c83c20619b3a6af93dfa4425969475ecc0 /src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | |
| parent | 6a936fc6ae0ba825f5830c072007c05db4242691 (diff) | |
| download | coreboot-0fec867e32a2df821e5a3569496b1dda7a2b1d5f.tar.gz coreboot-0fec867e32a2df821e5a3569496b1dda7a2b1d5f.tar.bz2 coreboot-0fec867e32a2df821e5a3569496b1dda7a2b1d5f.zip | |
soc/amd/picasso: add devicetree setting for PSPP policy
Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index a8c270e5fee5..252540093c80 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -250,6 +250,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end |