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| author | Raul E Rangel <rrangel@chromium.org> | 2022-07-29 21:07:36 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-08-10 17:13:07 +0000 |
| commit | 30edb46e8ca3b4994fda31c74e496910f8218818 (patch) | |
| tree | d7a89029381a799f852f83c86e75752c67417476 /src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | |
| parent | 74bce48f1d445053b217913df79a77dfe286e893 (diff) | |
| download | coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.tar.gz coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.tar.bz2 coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.zip | |
mb/google/zork: Set vw_irq_polarity from low to high
The EC used on zork uses a level high interrupt. This change configures
the polarity correctly.
The eSPI config is baked into RO verstage. The zork ToT build doesn't
use signed verstage since it's incompatible with the ToT version of
vboot. This means we can safely switch the keyboard IRQ polarity.
NOTE: Do not cherry pick this into the Zork firmware branch!
BUG=b:160595155
TEST=On morphius verify keyboard works as correctly and no spurious
interrupts are thrown on S0i3 resume. Also verified keyboard and mouse
work correctly in windows.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 69146041e82f..68eb6ea5887e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -227,13 +227,7 @@ chip soc/amd/picasso .oob_ch_en = 0, .flash_ch_en = 0, - /* - * b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH, - * but eSPI gets configured in verstage which is in RO. - * We have already locked RO for zork devices so we need - * make it so x86 coreboot re-initializes the vw_irq_polarity. - */ - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), }" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" |