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| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:37:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:06:52 +0000 |
| commit | 50863daef8ed75c0cb3dfd375e7622c898de5821 (patch) | |
| tree | cbb2dea518524f8c9ce5edca5d57132ca9705086 /src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | |
| parent | 0949e739066c3509e05db2b9ed71cefaaa62205f (diff) | |
| download | coreboot-50863daef8ed75c0cb3dfd375e7622c898de5821.tar.gz coreboot-50863daef8ed75c0cb3dfd375e7622c898de5821.tar.bz2 coreboot-50863daef8ed75c0cb3dfd375e7622c898de5821.zip | |
src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 947672373507..68eb6ea5887e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD |