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| author | Raul E Rangel <rrangel@chromium.org> | 2021-12-06 12:15:45 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-08 00:50:48 +0000 |
| commit | 04cf42775cca3f300dc3e8240bc70e706f091ca0 (patch) | |
| tree | 6e4a5fae2f5c9c4736af33706e91113f7bc7ae44 /src/mainboard/google/zork/variants/baseboard/include | |
| parent | 6ebcdf38724bd1c89cb5e769b54cb50b302b3062 (diff) | |
| download | coreboot-04cf42775cca3f300dc3e8240bc70e706f091ca0.tar.gz coreboot-04cf42775cca3f300dc3e8240bc70e706f091ca0.tar.bz2 coreboot-04cf42775cca3f300dc3e8240bc70e706f091ca0.zip | |
mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init
These functions can't be weak, because they actually need to configure
the GPIOs for eSPI and the TPM. With this change zork boots again.
I also noticed that zork doesn't use the early table in bootblock. This
means that zork will only boot if psp_verstage is enabled.
BUG=b:209465425
TEST=boot zork to ramstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/include')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 3f7e5d1c340d..38c5d4ad2786 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -33,6 +33,12 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_ty */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + void variant_updm_update(FSP_M_CONFIG *mcfg); /* Program any required GPIOs at the finalize phase */ |