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| author | Furquan Shaikh <furquan@google.com> | 2020-08-04 20:16:55 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-08-06 19:09:03 +0000 |
| commit | cc6c41f8d8b6880a7ad4947599350758cd18f85f (patch) | |
| tree | d47ce96bb7a3c021e11d59b55078859475d293a4 /src/mainboard/google/zork/variants/berknip | |
| parent | 55fefbe39d9637e93031efe7b59746df8ebf733a (diff) | |
| download | coreboot-cc6c41f8d8b6880a7ad4947599350758cd18f85f.tar.gz coreboot-cc6c41f8d8b6880a7ad4947599350758cd18f85f.tar.bz2 coreboot-cc6c41f8d8b6880a7ad4947599350758cd18f85f.zip | |
mb/google/zork: Switch USI_RESET to active low polarity for v3.6+
v3.6 of reference schematics have switched the polarity of reset
signal to touchscreen controller from active high to active low. This
change updates the default configuration in baseboard gpio tables to
set the reset GPIO to output low and override tables in variants to set the
reset GPIO to output high. Additionally, devicetree by default exposes
ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6
boards, reset GPIO is updated to ACTIVE_HIGH based on board version.
BUG=b:161937506
Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/berknip')
| -rw-r--r-- | src/mainboard/google/zork/variants/berknip/gpio.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index 08b1c4da244b..2a43b5a19039 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -22,6 +22,13 @@ static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = { PAD_GPI(GPIO_86, PULL_NONE), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio berknip_bid2_gpio_set_stage_ram[] = { + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -39,6 +46,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) if (board_version <= 1) { *size = ARRAY_SIZE(berknip_bid1_gpio_set_stage_ram); return berknip_bid1_gpio_set_stage_ram; + } else if (board_version <= 2) { + *size = ARRAY_SIZE(berknip_bid2_gpio_set_stage_ram); + return berknip_bid2_gpio_set_stage_ram; } *size = 0; |