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authorFurquan Shaikh <furquan@google.com>2020-08-04 20:16:55 -0700
committerFurquan Shaikh <furquan@google.com>2020-08-06 19:09:03 +0000
commitcc6c41f8d8b6880a7ad4947599350758cd18f85f (patch)
treed47ce96bb7a3c021e11d59b55078859475d293a4 /src/mainboard/google/zork/variants/dirinboz
parent55fefbe39d9637e93031efe7b59746df8ebf733a (diff)
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mb/google/zork: Switch USI_RESET to active low polarity for v3.6+
v3.6 of reference schematics have switched the polarity of reset signal to touchscreen controller from active high to active low. This change updates the default configuration in baseboard gpio tables to set the reset GPIO to output low and override tables in variants to set the reset GPIO to output high. Additionally, devicetree by default exposes ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6 boards, reset GPIO is updated to ACTIVE_HIGH based on board version. BUG=b:161937506 Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/dirinboz')
-rw-r--r--src/mainboard/google/zork/variants/dirinboz/Makefile.inc2
-rw-r--r--src/mainboard/google/zork/variants/dirinboz/gpio.c34
2 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc
index 9dc5159c5362..0b6bc4b3494a 100644
--- a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc
+++ b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
subdirs-y += ../baseboard/spd
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c
new file mode 100644
index 000000000000..7269b23db54c
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+ /* USI_RESET */
+ PAD_GPO(GPIO_140, HIGH),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+ uint32_t board_version;
+
+ /*
+ * If board version cannot be read, assume that this is an older revision of the board
+ * and so apply overrides. If board version is provided by the EC, then apply overrides
+ * if version < 2.
+ */
+ if (google_chromeec_cbi_get_board_version(&board_version))
+ board_version = 1;
+
+ if (board_version < 2) {
+ *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
+ return bid_1_gpio_set_stage_ram;
+ }
+
+ *size = 0;
+ return NULL;
+}