diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2022-07-29 21:07:36 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-08-10 17:13:07 +0000 |
| commit | 30edb46e8ca3b4994fda31c74e496910f8218818 (patch) | |
| tree | d7a89029381a799f852f83c86e75752c67417476 /src/mainboard/google/zork/variants/morphius/include/variant/ec.h | |
| parent | 74bce48f1d445053b217913df79a77dfe286e893 (diff) | |
| download | coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.tar.gz coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.tar.bz2 coreboot-30edb46e8ca3b4994fda31c74e496910f8218818.zip | |
mb/google/zork: Set vw_irq_polarity from low to high
The EC used on zork uses a level high interrupt. This change configures
the polarity correctly.
The eSPI config is baked into RO verstage. The zork ToT build doesn't
use signed verstage since it's incompatible with the ToT version of
vboot. This means we can safely switch the keyboard IRQ polarity.
NOTE: Do not cherry pick this into the Zork firmware branch!
BUG=b:160595155
TEST=On morphius verify keyboard works as correctly and no spurious
interrupts are thrown on S0i3 resume. Also verified keyboard and mouse
work correctly in windows.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/morphius/include/variant/ec.h')
| -rw-r--r-- | src/mainboard/google/zork/variants/morphius/include/variant/ec.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h index 3564d542cd31..fbcdf4e0f895 100644 --- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -4,6 +4,7 @@ /* Enable PS/2 Mouse */ #define SIO_EC_ENABLE_PS2M +#define SIO_EC_PS2M_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {12} /* Enable DPTC support */ #define EC_ENABLE_AMD_DPTC_SUPPORT |