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| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2023-07-28 11:27:32 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-31 13:56:18 +0000 |
| commit | 27830d0ec375e49e7e0cb4e26bbc03ea5c3d5a84 (patch) | |
| tree | a008160fce49f1bd521c95321750a22cd8ea9ed5 /src/mainboard/google | |
| parent | 91f5da477677cc6a7a7d5cdc50f5d2bf71981e44 (diff) | |
| download | coreboot-27830d0ec375e49e7e0cb4e26bbc03ea5c3d5a84.tar.gz coreboot-27830d0ec375e49e7e0cb4e26bbc03ea5c3d5a84.tar.bz2 coreboot-27830d0ec375e49e7e0cb4e26bbc03ea5c3d5a84.zip | |
mb/google/brya/var/vell: Disable PCH USB2 phy power gating
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for vell board. Please refer Intel doc#723158 for
more information.
BUG=b:293535284
TEST=build and boot vell
Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 5298a7e3582f..c024796e62f3 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -71,6 +71,10 @@ chip soc/intel/alderlake register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "sagv" = "SaGv_Enabled" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + # Set EPP to 50%: 50 * 256 / 100 = 0x80 register "enable_energy_perf_pref" = "true" register "energy_perf_pref_value" = "0x80" |