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| author | Subrata Banik <subrata.banik@intel.com> | 2021-01-27 16:34:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-01-28 04:09:39 +0000 |
| commit | 1476f6992a438ef540c0c1d997d3cd316d3179da (patch) | |
| tree | 87cf0ae461eb3ed1442d32caebbf03b5bef4876a /src/mainboard/intel/adlrvp/devicetree.cb | |
| parent | 1b8906a52984835698039740d39b83d2fa505997 (diff) | |
| download | coreboot-1476f6992a438ef540c0c1d997d3cd316d3179da.tar.gz coreboot-1476f6992a438ef540c0c1d997d3cd316d3179da.tar.bz2 coreboot-1476f6992a438ef540c0c1d997d3cd316d3179da.zip | |
mb/intel/adlrvp: Remove ClkReq assignment for RP8
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required.
TEST=Able to detect PCIe SD card over x1 slot.
Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index cf9afaf68c37..c18223ff478a 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -53,9 +53,7 @@ chip soc/intel/alderlake # Enable PCH PCIE RP 8 using CLK 6 register "PchPcieRpEnable[7]" = "1" - register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6 register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK - register "PcieRpClkReqDetect[6]" = "1" # Enable PCH PCIE RP 9 using CLK 1 register "PchPcieRpEnable[8]" = "1" |