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authorSubrata Banik <subratabanik@google.com>2022-01-03 19:17:34 +0000
committerFelix Held <felix-coreboot@felixheld.de>2022-01-25 16:12:33 +0000
commit7f8ab005ca20bdd70368de1c4f4dcfea5a42ff86 (patch)
treea9593eb1efb597c2d82a705ab0e7a89e6ac9182c /src/mainboard/intel/adlrvp/devicetree.cb
parentff99f1246fb427edbd2741a05ba3155c3ba7b3c4 (diff)
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soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 8f60e4297003..9bd99b18f762 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -8,9 +8,6 @@ chip soc/intel/alderlake
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 interface
- register "HeciEnabled" = "1"
-
# FSP configuration
# Enable CNVi BT