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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-02 23:29:07 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-05 13:21:55 +0000 |
| commit | f9891c8b469232cca28f0b12f613274f127748df (patch) | |
| tree | b10131ca552bcce69e92490a5f4a76575405387a /src/mainboard/kontron/986lcd-m/romstage.c | |
| parent | ad787e18e0ed24495132d0e9e638ed835afad354 (diff) | |
| download | coreboot-f9891c8b469232cca28f0b12f613274f127748df.tar.gz coreboot-f9891c8b469232cca28f0b12f613274f127748df.tar.bz2 coreboot-f9891c8b469232cca28f0b12f613274f127748df.zip | |
kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset
The extra PCI bus RST# and 200ms delay there was workaround
for custom add-on hardware.
Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/romstage.c')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c0e60713011a..7fa1b4271eeb 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -245,9 +245,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# to conventional PCI slot and Firewire. */ - ich7_p2p_secondary_reset(); - ich7_enable_lpc(); early_superio_config_w83627thg(); |