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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-11-22 11:40:01 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-24 06:04:03 +0000 |
| commit | 0f633f7f7f1ff38f9f55d98fd0c5e5c26b2a2e07 (patch) | |
| tree | 7cacf700059475060269027325987d53b5a7533c /src/mainboard/siemens | |
| parent | 16dd1c31c22d56e53d4e37c66c52e1177f6c38f2 (diff) | |
| download | coreboot-0f633f7f7f1ff38f9f55d98fd0c5e5c26b2a2e07.tar.gz coreboot-0f633f7f7f1ff38f9f55d98fd0c5e5c26b2a2e07.tar.bz2 coreboot-0f633f7f7f1ff38f9f55d98fd0c5e5c26b2a2e07.zip | |
mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs
Set downshift counter to 2 for all Marvell PHYs on this mainboard before
the PHY downshifts to the next highest speed.
Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 8090927661c4..e1c297274ce9 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -191,6 +191,7 @@ chip soc/intel/elkhartlake register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 0 on # PHY address ops m88e1512_ops end @@ -206,6 +207,7 @@ chip soc/intel/elkhartlake register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end @@ -224,6 +226,7 @@ chip soc/intel/elkhartlake register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end |