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| author | Jan Samek <jan.samek@siemens.com> | 2022-12-16 13:21:11 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-21 13:50:25 +0000 |
| commit | 12b2a3a477556764f6d7a7629d02b9abad3f58f0 (patch) | |
| tree | 473b15577259104119b4b90dd37c80f27fa3a534 /src/mainboard/siemens | |
| parent | 37cb9223746c1dba8bbd2e16a8b95c6048a0dea9 (diff) | |
| download | coreboot-12b2a3a477556764f6d7a7629d02b9abad3f58f0.tar.gz coreboot-12b2a3a477556764f6d7a7629d02b9abad3f58f0.tar.bz2 coreboot-12b2a3a477556764f6d7a7629d02b9abad3f58f0.zip | |
mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaks
Contrary to mc_ehl2, which this variant is based on, this board
doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the
attempts to modify the bridge's registers unnecessary.
Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c index 339516057a6d..37eb7aecf36c 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c @@ -2,12 +2,10 @@ #include <baseboard/variants.h> #include <bootstate.h> -#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <gpio.h> -#include <intelblocks/pcr.h> #include <soc/gpio.h> #include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #define HOSTCTRL2 0x3E #define HOSTCTRL2_PRESET (1 << 15) @@ -22,15 +20,6 @@ void variant_mainboard_final(void) { struct device *dev; - /* PIR8 register mapping for PCIe root ports - INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ - pcr_write16(PID_ITSS, 0x3150, 0x1032); - - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to layout limitations. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); |