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| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-23 11:00:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-29 09:13:27 +0000 |
| commit | 5384da40b205b0088b1430bce3ab1cc014aeb286 (patch) | |
| tree | 0703f9b3e0f70805f48eccf02eb277a0d463dcda /src/mainboard/siemens | |
| parent | 2a174f16d9efad0640995a69cbd212ae79b06be2 (diff) | |
| download | coreboot-5384da40b205b0088b1430bce3ab1cc014aeb286.tar.gz coreboot-5384da40b205b0088b1430bce3ab1cc014aeb286.tar.bz2 coreboot-5384da40b205b0088b1430bce3ab1cc014aeb286.zip | |
mb/siemens/mc_ehl1: Enable In Band ECC
Enable IBECC for mc_ehl1 to provide a memory failure protection.
Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 34a4ce596bda..1eece7aeed20 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -20,6 +20,12 @@ chip soc/intel/elkhartlake register "SmbusEnable" = "1" register "Heci2Enable" = "1" + # Enable IBECC for the complete memory + register "ibecc" = "{ + .enable = 1, + .mode = IBECC_ALL + }" + # USB related UPDs register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 |