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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-11-24 08:38:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-25 15:44:46 +0000 |
| commit | 68fb5437f9680428cbb7cf39c4a73911671a6359 (patch) | |
| tree | a4ca0fe7503e7d241ed9f7550b76ffd7ddb92ffd /src/mainboard/siemens | |
| parent | 3627f2903c8597b8765117146cf2868daecfe305 (diff) | |
| download | coreboot-68fb5437f9680428cbb7cf39c4a73911671a6359.tar.gz coreboot-68fb5437f9680428cbb7cf39c4a73911671a6359.tar.bz2 coreboot-68fb5437f9680428cbb7cf39c4a73911671a6359.zip | |
mb/siemens/mc_ehl2: Disable L1 prefetcher
As for mainboard mc_ehl1, a hard real-time dependency is also required
for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive
which in the end leads to an increased number of cache misses. Disabling
the L1 prefetcher boosts up the performance (in some cases by more than
10 %) in this specific use case.
Change-Id: I07b27dd672533e693a6c2987d16f54333850760e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index e1c297274ce9..74d0f26e42da 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -135,6 +135,9 @@ chip soc/intel/elkhartlake .vcc_low_high_us = 50, }" + # Disable L1 prefetcher for real-time demands + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |