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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-06 12:19:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-07 16:47:36 +0000 |
| commit | f76acba3bfa8c216bc7deb09e39a9cd7ba4672c0 (patch) | |
| tree | 5a1ed4096b06c813dbeef82a6225ca2d6f79db8a /src/mainboard/siemens | |
| parent | 87f883959dee771d66e441e134111ba7b76b4ac5 (diff) | |
| download | coreboot-f76acba3bfa8c216bc7deb09e39a9cd7ba4672c0.tar.gz coreboot-f76acba3bfa8c216bc7deb09e39a9cd7ba4672c0.tar.bz2 coreboot-f76acba3bfa8c216bc7deb09e39a9cd7ba4672c0.zip | |
siemens/mc_apl3: Enable all PCIe root ports
Enable all PCIe root ports for this mainboard.
Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index bb3bf6f2faa9..36d4dbb20d04 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -59,12 +59,12 @@ chip soc/intel/apollolake device pci 0e.0 off end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY - device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY - device pci 13.2 off end # - RP 4 - PCIe-A 2 - device pci 13.3 off end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 on end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 on end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 |