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| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 19:12:55 +0000 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:33:14 +0000 |
| commit | ad50b40eed3f7f235e848a2382ffbee6a51d1755 (patch) | |
| tree | b8791e9c965c0b89d92e6d70d1635b99e184ba7a /src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb | |
| parent | a2f51f222549035b27578cb084e13219443ca4b6 (diff) | |
| download | coreboot-ad50b40eed3f7f235e848a2382ffbee6a51d1755.tar.gz coreboot-ad50b40eed3f7f235e848a2382ffbee6a51d1755.tar.bz2 coreboot-ad50b40eed3f7f235e848a2382ffbee6a51d1755.zip | |
soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb')
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index fb559d284e03..66b8e86eb789 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -18,7 +18,6 @@ chip soc/intel/tigerlake register "CnviBtCore" = "true" register "CnviBtAudioOffload" = "1" register "enable_c6dram" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "TcssD3ColdDisable" = "1" |