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| author | Tim Crawford <tcrawford@system76.com> | 2022-09-29 12:11:34 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-02 15:53:49 +0000 |
| commit | 8e3787eaf01f84b449cca3d37ec584ad77228b86 (patch) | |
| tree | e8037b1d49f34f275b8c1516f19164367e986c9e /src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c | |
| parent | def33cc5bb4d37d1b7131c45ae064a648b88bdab (diff) | |
| download | coreboot-8e3787eaf01f84b449cca3d37ec584ad77228b86.tar.gz coreboot-8e3787eaf01f84b449cca3d37ec584ad77228b86.tar.bz2 coreboot-8e3787eaf01f84b449cca3d37ec584ad77228b86.zip | |
mb/system76/tgl-h: Convert oryp8 to a variant
Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c')
| -rw-r--r-- | src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c new file mode 100644 index 000000000000..72ad3fc5e7db --- /dev/null +++ b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // PEG0 Config + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // PEG1 Config + params->CpuPcieRpAdvancedErrorReporting[1] = 0; + params->CpuPcieRpLtrEnable[1] = 1; + params->CpuPcieRpPtmEnabled[1] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[8] = 1; // TYPEC1 + params->UsbTcPortEn = 1; + + // Low latency legacy I/O + params->PchLegacyIoLowLatency = 1; +} |