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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-08-07 07:27:57 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-08 17:51:16 +0000 |
| commit | bd4a3f8cd9ec4c59ad1d33102958e525a9c8c6ef (patch) | |
| tree | f796856ba45aa571fdf4c936c4333ee6643c5db3 /src/northbridge/amd | |
| parent | e13dd172b12a51472641939c42005d40d7328836 (diff) | |
| download | coreboot-bd4a3f8cd9ec4c59ad1d33102958e525a9c8c6ef.tar.gz coreboot-bd4a3f8cd9ec4c59ad1d33102958e525a9c8c6ef.tar.bz2 coreboot-bd4a3f8cd9ec4c59ad1d33102958e525a9c8c6ef.zip | |
cpu/amd: Correct number of MCA banks cleared
Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear. The generations should have the following
number of banks:
* Family 10h: 6 banks
* Family 12h: 6
* Family 14h: 6
* Family 15h: 7
* Family 16h: 6
Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdmct/amddefs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 03d9bb347791..977fd9c959df 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -128,6 +128,7 @@ #define CPUID_MODEL 1 #define MCG_CAP 0x00000179 #define MCG_CTL_P 8 + #define MCA_BANKS_MASK 0xff #define MC0_CTL 0x00000400 #define MC0_STA (MC0_CTL + 1) #define MC4_MISC0 0x00000413 |