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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-09-13 09:55:49 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-14 12:01:24 +0000 |
| commit | 5e6b0f0cac4ba5cde6114325ea69ec0e98c7e08f (patch) | |
| tree | 06433b2873415812ac1fb28c51819cd89e4caa74 /src/northbridge/intel/gm45/northbridge.c | |
| parent | 1fac2e20b8161e1dc93086b4c5498548827f1604 (diff) | |
| download | coreboot-5e6b0f0cac4ba5cde6114325ea69ec0e98c7e08f.tar.gz coreboot-5e6b0f0cac4ba5cde6114325ea69ec0e98c7e08f.tar.bz2 coreboot-5e6b0f0cac4ba5cde6114325ea69ec0e98c7e08f.zip | |
nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index f41adf32be18..1078748de655 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -174,7 +174,7 @@ void northbridge_write_smram(u8 smram) { struct device *dev = pcidev_on_root(0, 0); - if (dev == NULL) + if (!dev) die("could not find pci 00:00.0!\n"); pci_write_config8(dev, D0F0_SMRAM, smram); |