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path: root/src/northbridge/intel/gm45/northbridge.c
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* device/device.h: Rename busses for clarityArthur Heymans2024-01-311-1/+1
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-311-1/+1
* device/device.h: Rename pci_domain_scan_busArthur Heymans2023-10-201-1/+1
* nb/intel/gm45: Rework nb resource readingArthur Heymans2023-07-141-46/+24
* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-051-0/+8
* nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-011-13/+2
* treewide: use predicate to check if pci device is on n-th busFabio Aiuto2022-10-061-1/+1
* nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas2022-09-141-1/+1
* nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki2022-07-051-6/+1
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-221-7/+7
* nb/intel/i945,gm45: Use incrementing index with fixed resourceKyösti Mälkki2022-05-241-7/+8
* nb/intel/gm45: Enable 64bit supportArthur Heymans2022-05-131-1/+1
* nb/intel/gm45: Allow for PCI BARs above 4GArthur Heymans2022-05-131-7/+35
* nb/intel/gm45: Define and use MMCONF_BUS_NUMBERAngel Pons2021-01-301-39/+1
* nb/intel/gm45: Reserve MMIO and firmware memory below 1MiBNico Huber2021-01-181-15/+18
* nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons2020-08-041-1/+1
* nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons2020-08-041-3/+4
* nb/intel/gm45: Use PCI bitwise opsAngel Pons2020-08-041-5/+5
* nb/intel: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS2020-05-261-5/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-021-1/+1
* Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber2020-04-101-2/+2
* Drop unnecessary DEVICE_NOOP entriesNico Huber2020-04-101-1/+0
* src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* Drop explicit NULL initializations from `device_operations`Elyes HAOUAS2020-04-051-2/+0
* Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber2020-04-021-1/+1
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-1/+0
* northbridge: Remove unused include <device/pci.h>Elyes HAOUAS2020-03-061-1/+0
* northbridge: Add missing include <device/pci_def.h>Elyes HAOUAS2019-12-311-0/+1
* src/northbridge: Remove unused <stdlib.h>Elyes HAOUAS2019-12-191-1/+0
* src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS2019-10-281-1/+0
* intel/smm/gen1: Rename header fileKyösti Mälkki2019-08-151-1/+1
* cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki2019-08-151-7/+1
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+1
* src: Drop unused include <arch/acpi.h>Elyes HAOUAS2019-03-061-1/+0
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* nb/intel/gm45: Use parallel MP initArthur Heymans2019-01-231-21/+1
* device: Use pcidev_on_root()Kyösti Mälkki2019-01-061-5/+5
* device: Replace ugly cases of dev_find_slot()Kyösti Mälkki2019-01-041-1/+1
* northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS2018-12-191-1/+0
* nb/intel/gm45: Correctly cache TSEGArthur Heymans2018-12-031-16/+0
* nb/intel/gm45/northbridge.c: Check for NULL pointersArthur Heymans2018-11-251-3/+12
* src: Get rid of duplicated includesElyes HAOUAS2018-11-161-1/+0
* nb/intel/*: Account for cbmem_top alignmentArthur Heymans2018-10-241-1/+11
* nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans2018-08-011-7/+11
* nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans2018-07-301-0/+38
* sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans2018-06-291-0/+17
* {mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber2018-05-081-1/+0
* nb/intel/gm45: Get rid of device_tElyes HAOUAS2018-04-301-6/+6
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