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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 11:46:58 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 12:22:04 +0000 |
| commit | b053583a1c372a0b7018241a5e6bd2d8d00b843c (patch) | |
| tree | 5d5d54ef630bef5d67766bc425583cba99d0ebf3 /src/northbridge/intel/gm45/northbridge.c | |
| parent | e16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d (diff) | |
| download | coreboot-b053583a1c372a0b7018241a5e6bd2d8d00b843c.tar.gz coreboot-b053583a1c372a0b7018241a5e6bd2d8d00b843c.tar.bz2 coreboot-b053583a1c372a0b7018241a5e6bd2d8d00b843c.zip | |
nb/intel/gm45: Use PCI bitwise ops
While we are at it, also reflow a few lines that fit in 96 characters.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index b3dbe16b7560..0308e216c7b1 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -259,12 +259,12 @@ static void gm45_init(void *const chip_info) break; } for (; fn >= 0; --fn) { - const struct device *const d = - pcidev_on_root(dev, fn); - if (!d || d->enabled) continue; - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + const struct device *const d = pcidev_on_root(dev, fn); + if (!d || d->enabled) + continue; + /* FIXME: Using bitwise ops changes the binary */ pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); + pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn))); } } |