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| author | Nico Huber <nico.h@gmx.de> | 2019-08-11 19:53:56 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-26 13:40:58 +0000 |
| commit | 87b5fa7c9d291521223678c1f9d9ee5c0c3444e5 (patch) | |
| tree | 45aec770bd7775e3bb794e76bc537404949420f9 /src/northbridge/intel/gm45/raminit_receive_enable_calibration.c | |
| parent | d13118320030c6df48ad33243d48c3ff34cb67d7 (diff) | |
| download | coreboot-87b5fa7c9d291521223678c1f9d9ee5c0c3444e5.tar.gz coreboot-87b5fa7c9d291521223678c1f9d9ee5c0c3444e5.tar.bz2 coreboot-87b5fa7c9d291521223678c1f9d9ee5c0c3444e5.zip | |
nb/intel/gm45: Add remaining raminit code to support DDR2
Add the remaining DDR2 code to program the registers for memory
timings, ODT, RCOMP, and refresh mode; and perform receive-enable
calibration.
TEST: DDR2 systems boot
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I6d9a1853fea9e29171d7c2f9ffe7086685c9efad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/raminit_receive_enable_calibration.c')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit_receive_enable_calibration.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 6ca801337f64..755839b46caa 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -185,7 +185,8 @@ static void find_preamble(const int channel, const int group, } } -static void receive_enable_calibration(const timings_t *const timings, +static void receive_enable_calibration(const int ddr_type, + const timings_t *const timings, const dimminfo_t *const dimms) { /* Override group to byte-lane mapping for raw card type F DIMMS. */ @@ -200,7 +201,8 @@ static void receive_enable_calibration(const timings_t *const timings, }; const unsigned int t_bound = - (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12; + (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 + : (ddr_type == DDR3) ? 12 : 15; const unsigned int p_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; @@ -259,7 +261,8 @@ static void receive_enable_calibration(const timings_t *const timings, } } -void raminit_receive_enable_calibration(const timings_t *const timings, +void raminit_receive_enable_calibration(const int ddr_type, + const timings_t *const timings, const dimminfo_t *const dimms) { int ch; @@ -284,7 +287,7 @@ void raminit_receive_enable_calibration(const timings_t *const timings, mchbar_clrsetbits32(0x14f0, 3 << 9, 1 << 9); mchbar_clrsetbits32(0x15f0, 3 << 9, 1 << 9); - receive_enable_calibration(timings, dimms); + receive_enable_calibration(ddr_type, timings, dimms); mchbar_clrbits32(0x12a4, 1 << 31); mchbar_clrbits32(0x13a4, 1 << 31); |