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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-10 19:22:31 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:38:29 +0000 |
| commit | 11c6b8b53182c5c83095136712f3d38eb5c1dd6a (patch) | |
| tree | 71bf26998c487dd0528cd7f720e2b385be93e211 /src/northbridge/intel/haswell/northbridge.c | |
| parent | b8b41338aae9acfa2a49c64d8e57a95653aef610 (diff) | |
| download | coreboot-11c6b8b53182c5c83095136712f3d38eb5c1dd6a.tar.gz coreboot-11c6b8b53182c5c83095136712f3d38eb5c1dd6a.tar.bz2 coreboot-11c6b8b53182c5c83095136712f3d38eb5c1dd6a.zip | |
nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMIC
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c00c801ee193..501caf17f11c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -14,7 +14,6 @@ #include <boot/tables.h> #include <security/intel/txt/txt_register.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" #include "haswell.h" @@ -336,9 +335,6 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (CONFIG(CHROMEOS_RAMOOPS)) - chromeos_reserve_ram_oops(dev, index++); - *resource_cnt = index; } |