summaryrefslogtreecommitdiffstats
path: root/src/northbridge/intel/haswell/northbridge.c
Commit message (Expand)AuthorAgeFilesLines
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-311-1/+1
* device/device.h: Rename pci_domain_scan_busArthur Heymans2023-10-201-1/+1
* nb/haswell: Use newer function for resource declarationsArthur Heymans2023-07-171-40/+19
* treewide: Remove duplicated include <device/pci.h>Elyes Haouas2023-02-011-1/+0
* cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans2022-11-251-1/+1
* nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans2022-11-091-13/+2
* treewide: use predicate to check if pci device is on n-th busFabio Aiuto2022-10-061-1/+1
* nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki2022-07-051-6/+2
* device/resource: Modify some resource allocation instancesKyösti Mälkki2022-06-241-4/+4
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-221-7/+7
* src: Make PCI ID define names shorterFelix Singer2022-03-071-1/+1
* Spell *Boot Guard* with a space for official spellingPaul Menzel2021-12-161-1/+1
* nb/intel/haswell/northbridge.c: Drop stale commentAngel Pons2021-11-051-4/+0
* src/mainboard to src/security: Fix spelling errorsMartin Roth2021-10-051-1/+1
* nb/intel/haswell/memmap.h: Define MMIO window sizesAngel Pons2021-06-161-7/+5
* nb/intel: Replace remaining BAR accessorsAngel Pons2021-04-101-18/+4
* nb/intel/haswell: Use new fixed BAR accessorsAngel Pons2021-04-101-76/+48
* nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`Angel Pons2021-03-281-4/+8
* nb/intel/haswell: Finalize northbridge in ramstageAngel Pons2021-03-101-0/+33
* nb/intel/haswell: Indent PCI ops with tabsAngel Pons2021-03-071-5/+5
* nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak2021-03-011-2/+2
* nb/intel/haswell/northbridge.c: Correct DPR handlingAngel Pons2021-02-241-14/+11
* nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG writeAngel Pons2021-02-181-3/+0
* nb/intel: Add missing <types.h>Elyes HAOUAS2021-02-161-1/+1
* nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki2021-02-161-4/+0
* nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()Kyösti Mälkki2021-02-161-5/+4
* nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons2021-02-121-3/+3
* intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons2021-02-051-1/+1
* nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons2021-01-301-41/+2
* nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons2021-01-271-0/+1
* {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons2020-10-311-3/+3
* nb/intel/haswell: Generalise northbridge chip nameAngel Pons2020-10-241-1/+1
* nb/intel/haswell: Set up Root Complex topologyAngel Pons2020-10-241-0/+65
* nb/intel/haswell: Account for DPR region in memory mapAngel Pons2020-10-151-3/+22
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-041-0/+5
* nb/intel/haswell: Add Crystal Well PCI IDsIru Cai2020-08-031-0/+3
* nb/intel/haswell: Configure VCs on Egress PortAngel Pons2020-07-311-0/+17
* nb/intel/haswell: Enable DMI ASPMAngel Pons2020-07-281-0/+42
* src: Use pci_dev_ops_pci where applicableAngel Pons2020-06-061-5/+1
* src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS2020-06-061-1/+0
* device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel2020-05-121-5/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* nb/intel/haswell/northbridge.c: Fix typoAngel Pons2020-05-081-1/+1
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-021-1/+1
* Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber2020-04-101-2/+2
* Drop unnecessary DEVICE_NOOP entriesNico Huber2020-04-101-1/+0
* src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* Drop explicit NULL initializations from `device_operations`Elyes HAOUAS2020-04-051-4/+0
* Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber2020-04-021-7/+7
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 21:53:21 +0000