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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-29 21:52:00 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-18 10:10:54 +0000 |
| commit | 805ff571e3ba01f1935da9d5c72d00fd12d020ad (patch) | |
| tree | dcf1c7c22010b262afc36b8991a20acaaeefadc4 /src/northbridge/intel/haswell/northbridge.c | |
| parent | 2fa838dbab090f9842042f44330dea4558814c51 (diff) | |
| download | coreboot-805ff571e3ba01f1935da9d5c72d00fd12d020ad.tar.gz coreboot-805ff571e3ba01f1935da9d5c72d00fd12d020ad.tar.bz2 coreboot-805ff571e3ba01f1935da9d5c72d00fd12d020ad.zip | |
nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG write
This write was copied from Sandy Bridge. Neither Haswell reference code
nor Broadwell perform this write. Therefore, it seems safe to remove it.
Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c59dce792f2c..130c0ff8ac50 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -547,9 +547,6 @@ static void northbridge_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit. */ mdelay(1); set_power_limits(28); - - /* Set here before graphics PM init. */ - MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } static struct device_operations mc_ops = { |