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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 12:24:19 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-31 10:08:59 +0000 |
| commit | f5dd7b6eb9b247486406f387c1cdc8c893a8cdf4 (patch) | |
| tree | 91bf20fbeb079c82c03d3e5395873abd461b17d4 /src/northbridge/intel/haswell/northbridge.c | |
| parent | 8963f7d40be4961e8ae6dca4185e4e682ba2fdb9 (diff) | |
| download | coreboot-f5dd7b6eb9b247486406f387c1cdc8c893a8cdf4.tar.gz coreboot-f5dd7b6eb9b247486406f387c1cdc8c893a8cdf4.tar.bz2 coreboot-f5dd7b6eb9b247486406f387c1cdc8c893a8cdf4.zip | |
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd710f353..2d19ccdda5db 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 * switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; |