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authorAngel Pons <th3fanbus@gmail.com>2023-02-07 15:03:07 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-21 23:34:02 +0000
commit08391d2f5ffea38aa95152c53492f72261786714 (patch)
tree2bfc9ea57a224eb612bc52651fdb66cc1fe51e12 /src/northbridge/intel/haswell/pcie.c
parent6b7b4001930afa9f09273809df7501277f47e793 (diff)
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nb/intel/haswell/pcie.c: Make UBSAN not complain
UBSAN complains about "shift out of bounds", likely because integer literals are signed by default and the result of the operation will shift into the sign bit, yielding a negative value. However, as the negative value is then casted to an unsigned type, it works anyway. To make UBSAN happy, make sure the two troublesome integer literals are unsigned so that there's no sign bit to shift into. Tested on out-of-tree Asrock Z97 Extreme6, UBSAN now dies elsewhere. Link: https://ticket.coreboot.org/issues/449 Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72806 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/pcie.c')
-rw-r--r--src/northbridge/intel/haswell/pcie.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c
index e8d146b9df6d..7fe57e9eddf7 100644
--- a/src/northbridge/intel/haswell/pcie.c
+++ b/src/northbridge/intel/haswell/pcie.c
@@ -82,7 +82,7 @@ static void peg_enable(struct device *dev)
uint32_t slotcap = pci_read_config32(dev, PEG_SLOTCAP);
/* Physical slot number (zero for ports connected to onboard devices) */
- slotcap &= ~(0x1fff << 19);
+ slotcap &= ~(0x1fffU << 19);
if (slot_implemented) {
uint16_t slot_number = peg_cfg->phys_slot_number & 0x1fff;
if (slot_number == 0) {
@@ -124,7 +124,7 @@ static void peg_enable(struct device *dev)
/* Select -3.5 dB de-emphasis */
pci_or_config32(dev, PEG_LCTL2, 1 << 6);
- pci_or_config32(dev, PEG_L0SLAT, 1 << 31);
+ pci_or_config32(dev, PEG_L0SLAT, 1U << 31);
pci_update_config32(dev, 0x250, ~(7 << 20), 2 << 20);