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| author | Angel Pons <th3fanbus@gmail.com> | 2022-02-14 12:55:31 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 23:39:12 +0000 |
| commit | d00cfcb0a1ec3669fdf3833cb3f2d11920bd622e (patch) | |
| tree | 813b9da2effb96132d349d9ab11e33c27b95be52 /src/northbridge/intel/ironlake/raminit.h | |
| parent | 34619178983c4af5a8d2f00c779f54e556e74b06 (diff) | |
| download | coreboot-d00cfcb0a1ec3669fdf3833cb3f2d11920bd622e.tar.gz coreboot-d00cfcb0a1ec3669fdf3833cb3f2d11920bd622e.tar.bz2 coreboot-d00cfcb0a1ec3669fdf3833cb3f2d11920bd622e.zip | |
nb/intel/ironlake/raminit_heci.c: Move to southbridge scope
HECI stuff is in the southbridge, so put the code in there. Rename the
file to match the name of the function it provides.
Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/raminit.h')
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h index 6dd07b3f2429..edfce51125ff 100644 --- a/src/northbridge/intel/ironlake/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -106,6 +106,4 @@ u16 get_max_timing(struct raminfo *info, int channel); void early_quickpath_init(struct raminfo *info, const u8 x2ca8); void late_quickpath_init(struct raminfo *info, const int s3resume); -void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size); - #endif /* RAMINIT_H */ |