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| author | Subrata Banik <subrata.banik@intel.com> | 2021-04-09 20:35:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-04-10 12:00:33 +0000 |
| commit | 8cbe43b8d73ba02fc771f8ea00f7ec4ab2e37f5b (patch) | |
| tree | f247394eb42fd4dcb5da95bbe004a2e45aa4bfc5 /src/northbridge/intel/ironlake | |
| parent | 7c25317093bfae2010e3cfb1981910d8592d8f70 (diff) | |
| download | coreboot-8cbe43b8d73ba02fc771f8ea00f7ec4ab2e37f5b.tar.gz coreboot-8cbe43b8d73ba02fc771f8ea00f7ec4ab2e37f5b.tar.bz2 coreboot-8cbe43b8d73ba02fc771f8ea00f7ec4ab2e37f5b.zip | |
soc/intel/alderlake: Skip D3Cold for TBT
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device
is in disconnected state.
Not adhering this recommendation is blocking the S0ix state transition.
BUG=b:183670327
TEST=S0ix state transition occurs with TBT disconnected.
Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/northbridge/intel/ironlake')
0 files changed, 0 insertions, 0 deletions