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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-23 17:25:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:44:51 +0000 |
| commit | 340e4b80904feb6c5c21497fc52966854fa5ee79 (patch) | |
| tree | 4026de0ec0cc41f51dd121a0be76642a8d0a286d /src/northbridge/intel/pineview/memmap.c | |
| parent | 44874482fec69a849b06c378aa3eb69e75425256 (diff) | |
| download | coreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.tar.gz coreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.tar.bz2 coreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.zip | |
lib/cbmem_top: Add a common cbmem_top implementation
This adds a common cbmem_top implementation to all coreboot target.
In romstage a static variable will be used to cache the result of
cbmem_top_romstage.
In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable
needs to be populated by the stage entry with the value passed via the
calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the
same implementation as will be used as in romstage.
Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/northbridge/intel/pineview/memmap.c')
| -rw-r--r-- | src/northbridge/intel/pineview/memmap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index b4fef6bc76ad..0aa70cdb3470 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -132,7 +132,7 @@ static uintptr_t northbridge_get_tseg_base(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; |