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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-20 19:41:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 12:56:03 +0000 |
| commit | ef90609cbb4229ccc242f67c48a8e14273bf0aac (patch) | |
| tree | bb1ce9a66ee7a0d0458365f284f15a028689816b /src/northbridge/intel/pineview/memmap.c | |
| parent | 183ad06f522b279328acb70dfba52d31f9ff9c91 (diff) | |
| download | coreboot-ef90609cbb4229ccc242f67c48a8e14273bf0aac.tar.gz coreboot-ef90609cbb4229ccc242f67c48a8e14273bf0aac.tar.bz2 coreboot-ef90609cbb4229ccc242f67c48a8e14273bf0aac.zip | |
src: capitalize 'RAM'
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/pineview/memmap.c')
| -rw-r--r-- | src/northbridge/intel/pineview/memmap.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 0aa70cdb3470..9fde9f7fdbe9 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -149,8 +149,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, |