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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 09:23:02 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:27:10 +0000 |
| commit | d52bfbb6aa822b8d5137bedef638a5214a07e4da (patch) | |
| tree | 871296097a8f332225302fd40d7bbdbd3e7251ff /src/northbridge/intel/sandybridge/chipset.cb | |
| parent | 634d88c413553bb4e483842032e14c078cb5f165 (diff) | |
| download | coreboot-d52bfbb6aa822b8d5137bedef638a5214a07e4da.tar.gz coreboot-d52bfbb6aa822b8d5137bedef638a5214a07e4da.tar.bz2 coreboot-d52bfbb6aa822b8d5137bedef638a5214a07e4da.zip | |
cpu/intel/sandybridge: Use enum for ACPI C states
Also remove the now unnecessary comments from the devicetree.
Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/chipset.cb')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index e7ade1977eec..16fab6d17a23 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -8,9 +8,9 @@ chip northbridge/intel/sandybridge device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "CPU_ACPI_C1" + register "acpi_c2" = "CPU_ACPI_C3" + register "acpi_c3" = "CPU_ACPI_C7" end end |