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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-03-16 16:27:49 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-03-23 16:13:42 +0000 |
| commit | 1a24d845663d682ff2f89d5848bdd9e0edcded2f (patch) | |
| tree | 1bb36d693235501a75e9a76008b495d6c618e6b3 /src/soc/amd/cezanne/Kconfig | |
| parent | 2bd4c98c42c63883fc5bca9e687d5f5fb7776ccb (diff) | |
| download | coreboot-1a24d845663d682ff2f89d5848bdd9e0edcded2f.tar.gz coreboot-1a24d845663d682ff2f89d5848bdd9e0edcded2f.tar.bz2 coreboot-1a24d845663d682ff2f89d5848bdd9e0edcded2f.zip | |
soc/amd/common/psp_verstage: Write postcodes after ESPI init
On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.
BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.
Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 81cf9748c622..48944c858f16 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -345,6 +345,14 @@ config PSP_DISABLE_POSTCODES help Disables the output of port80 post codes from PSP. +config PSP_POSTCODES_ON_ESPI + bool "Use eSPI bus for PSP post codes" + depends on !PSP_DISABLE_POSTCODES + default y + help + Select to send PSP port80 post codes on eSPI bus. + If not selected, PSP port80 codes will be sent on LPC bus. + config PSP_INIT_ESPI bool "Initialize eSPI in PSP Stage 2 Boot Loader" help |