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path: root/src/soc/amd/cezanne/Kconfig
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* soc/amd: Factor out gpp_clk_setup functionVarshit Pandya2024-02-101-0/+1
* soc/amd: drop unneeded data_fabric_set_mmio_npFelix Held2024-02-071-1/+0
* soc/amd: factor out non-CAR romstage to common codeFelix Held2024-01-201-0/+1
* soc/amd/common/acpi: factor out common MADT codeFelix Held2024-01-111-0/+1
* soc/amd/common: Move PCIe CLKREQ programming under fspMatt DeVillier2023-12-061-1/+1
* soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM configKarthikeyan Ramasubramanian2023-11-281-0/+1
* soc/amd/*/Kconfig: rework SPL optionsFelix Held2023-10-251-22/+1
* soc/amd: rework SPL file override and SPL fusing handlingFelix Held2023-10-041-7/+15
* soc/amd: introduce SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGIONFelix Held2023-09-181-0/+1
* soc/amd/cezanne: select ADD_FSP_BINARIES if USE_AMD_BLOBSMatt DeVillier2023-09-041-0/+1
* util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao2023-09-011-33/+0
* treewide: Get rid of "NO_DDRx" selectionElyes Haouas2023-08-091-3/+0
* soc/amd/common/acpimmio: factor out IO port access to PM registersFelix Held2023-07-171-0/+1
* soc/amd/cezanne/chip: use common data fabric domain resource codeFelix Held2023-06-071-0/+1
* soc/amd/common/block/cpu/Kconfig: drop FAM17H_19H suffix from TSC optionFelix Held2023-03-291-1/+1
* soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freqFelix Held2023-03-291-0/+1
* soc/amd: introduce and use get_uvolts_from_vid for SVI2 and SVI3Felix Held2023-03-271-0/+1
* soc/amd/cezanne: Set up SoC-specific XHCI definitionsRobert Zieba2023-03-091-0/+1
* soc/amd: factor out ACPI_SSDT_PSD_INDEPENDENT to common AMD ACPI KconfigFelix Held2023-03-081-8/+0
* soc/amd/cezanne/acpi: rework C state info table handlingFelix Held2023-03-081-0/+1
* soc/amd/cezanne/Kconfig: add VGA BIOS ID and file defaultsFelix Held2023-02-161-0/+11
* soc/amd: Use common reset code for CZN & MDN SoCsMartin Roth2023-02-041-0/+1
* soc/amd/cezanne: use common SMU S3/4/5 entry message codeFelix Held2023-01-131-0/+1
* soc/amd/cezanne: Use common fsp-s preloaderFred Reitberger2023-01-121-0/+1
* soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas2023-01-091-7/+4
* arch/x86/Kconfig: Move AMD stages arch to common codeArthur Heymans2022-11-141-7/+0
* soc/amd: Specify memory types supported by each chipMartin Roth2022-11-041-0/+5
* soc/amd/cezanne/Kconfig: Enable APOB_HASHFred Reitberger2022-10-281-0/+1
* soc/amd/cezanne: Factor out common GPP clk req codeRobert Zieba2022-10-261-0/+1
* soc/amd: factor out common eMMC codeFelix Held2022-10-141-0/+1
* soc/amd/{CZN,MDN,PCO}: Fix building with only single RW regionMatt DeVillier2022-10-071-1/+5
* soc/amd/cezanne/Kconfig: add defaults for FSP_M_FILE and FSP_S_FILEFelix Held2022-09-141-0/+14
* soc/amd/common/acpi/cppc: add nominal and minimum frequenciesFelix Held2022-08-171-0/+1
* soc/amd/cezanne,common: factor out CPPC code to common AMD SoC codeFelix Held2022-08-121-0/+1
* soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config optionFred Reitberger2022-07-161-0/+4
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
* soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held2022-06-211-3/+0
* soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier2022-06-211-1/+0
* arch/x86/Kconfig: Drop obsolete fixed ramstage symbolsArthur Heymans2022-04-011-4/+0
* soc/amd/common/psp_verstage: Write postcodes after ESPI initKarthikeyan Ramasubramanian2022-03-231-0/+8
* drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik2022-02-181-0/+3
* soc/amd/cezanne: Allow to specify SPL table path in KconfigZheng Bao2022-02-121-0/+14
* soc/amd/common/acp: introduce acp_gen1Fred Reitberger2022-02-111-1/+1
* soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel2022-02-081-1/+0
* soc/amd/*/i2c: factor out common I2C pad configurationFelix Held2022-02-031-0/+1
* soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPIRaul E Rangel2022-02-021-6/+4
* soc/amd/cezanne: Increase PRERAM_CBMEM_CONSOLE_SIZE to 0x2000Raul E Rangel2022-01-251-1/+1
* soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZERaul E Rangel2022-01-231-0/+6
* soc/amd/{picasso,cezanne}: Enable CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel2022-01-181-0/+1
* soc/amd/cezanne: Don't select CPU_INFO_V2 explicitlyNico Huber2021-12-131-1/+0
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