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| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-11-13 20:57:12 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-06 19:12:59 +0000 |
| commit | 6bb0f8aaa489e5f8da2818069623bc2f202a42ef (patch) | |
| tree | 1e93f565afee3de2987481b61b2afbd13ea06ee6 /src/soc/amd/cezanne/Kconfig | |
| parent | fca7fd2a7367f27f45d9b784719f984a1128b758 (diff) | |
| download | coreboot-6bb0f8aaa489e5f8da2818069623bc2f202a42ef.tar.gz coreboot-6bb0f8aaa489e5f8da2818069623bc2f202a42ef.tar.bz2 coreboot-6bb0f8aaa489e5f8da2818069623bc2f202a42ef.zip | |
soc/amd/common: Move PCIe CLKREQ programming under fsp
CLKREQ programming as currently implemented is completely dependent on
FSP DXIO descriptors, so move under common/fsp/pci and rename the
Kconfig to reflect the move.
TEST=build google/{guybrush, skyrim, myst}
Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 3700f187720a..9c15dd98945d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -55,7 +55,6 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER - select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 @@ -74,6 +73,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_BLOCK_XHCI select SSE2 |