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path: root/src/soc/amd/cezanne/Kconfig
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* soc/amd/cezanne: Enable secure countersKarthikeyan Ramasubramanian2021-12-031-0/+1
* cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPISubrata Banik2021-11-291-1/+1
* lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel2021-11-161-1/+0
* sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMARaul E Rangel2021-11-131-1/+2
* soc/amd/cezanne: Use LZ4 for FSP-SRaul E Rangel2021-11-121-1/+1
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-101-2/+2
* soc/amd/cezanne: Enable CBFS_PRELOADRaul E Rangel2021-11-081-0/+5
* soc/amd/cezanne: Add ASYNC_FILE_LOADINGRaul E Rangel2021-11-081-3/+11
* Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUERaul E Rangel2021-11-041-1/+0
* cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans2021-11-031-4/+0
* arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki2021-10-221-1/+0
* Revert "soc/amd/cezanne: Disable Co-op multitasking"Raul E Rangel2021-10-051-0/+3
* soc/amd/cezanne: Enable CCP DMAKarthikeyan Ramasubramanian2021-09-271-0/+1
* soc/amd/cezanne: Increase the FSP_M_SIZE configurationKarthikeyan Ramasubramanian2021-09-011-2/+2
* soc/amd/cezanne: Disable Co-op multitaskingRaul E Rangel2021-08-181-2/+0
* soc/amd/cezanne: Generate IVRS for cezanneJason Glenesk2021-08-051-0/+1
* soc/amd/{cezanne,picasso}: Escape PSP_VERSTAGE_FILE defaultRaul E Rangel2021-07-191-1/+1
* soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHERaul E Rangel2021-07-191-0/+1
* soc/amd/cezanne: Start loading APOB asynchronouslyRaul E Rangel2021-07-181-0/+2
* soc/amd: factor out check_mca to common codeFelix Held2021-07-141-0/+1
* soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel2021-07-121-0/+1
* soc/amd/cezanne: Enable SPI DMA supportRaul E Rangel2021-07-021-0/+1
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-021-0/+3
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-301-0/+1
* soc/amd/cezanne: Supply SMBIOS/DMI Type 17 dataNikolai Vyssotski2021-06-131-0/+1
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-071-1/+0
* soc/amd: reduce MCACHE size with psp_verstageKangheui Won2021-05-221-0/+4
* soc/amd/cezanne/root_complex: generate DPTC ACPI methodFelix Held2021-05-131-0/+1
* soc/amd{common,cezanne}: Move pcie_gpp.c to commonRaul E Rangel2021-05-121-0/+1
* cezanne/psp_verstage: populate a/b firmwareKangheui Won2021-05-101-0/+18
* soc/amd/cezanne: Populate PCI_INTR registersRaul E Rangel2021-05-091-0/+1
* soc/amd/cezanne: Enable Audio Co-processor driverKarthikeyan Ramasubramanian2021-04-291-0/+1
* soc/amd/cezanne: copy Kconfig options for psp_verstageKangheui Won2021-04-281-1/+72
* soc/amd/cezanne,picasso/Kconfig: add help text for MAX_CPUSFelix Held2021-04-261-0/+2
* soc/amd/cezanne & picasso: Add Kconfig for hardcoded Soft Fuse bitsMartin Roth2021-04-261-0/+14
* guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes2021-04-221-0/+13
* soc/amd/cezanne/Kconfig: add missing ACPI_BERT and ACPI_BERT_SIZEFelix Held2021-04-181-0/+16
* soc/amd/cezanne: Port ACPI p-state and c-state entries from picassoJason Glenesk2021-04-161-0/+8
* soc/amd/cezanne: Select VBNV_CMOSRaul E Rangel2021-04-161-0/+4
* soc/amd/cezanne: save chipset state to CBMEMMartin Roth2021-04-141-0/+1
* soc/amd/cezanne: Set Power state after power failureKarthikeyan Ramasubramanian2021-04-101-0/+1
* soc/amd/cezanne: Add GRXS and GTXS methodEric Lai2021-04-101-0/+1
* soc/amd/cezanne: Enable GENERIC_GPIO_LIBRaul E Rangel2021-04-011-0/+1
* soc/amd: add DISABLE_KEYBOARD_RESET_PIN optionFelix Held2021-03-291-0/+8
* soc/amd/cezanne: Implement PROVIDES_ROM_SHARINGRaul E Rangel2021-03-291-0/+9
* soc/amd/cezanne: select HAVE_EM100_SUPPORTFelix Held2021-03-231-0/+1
* soc/amd/cezanne: Initialize I2CZheng Bao2021-03-221-0/+5
* soc/amd/cezanne: Get I2C specific code for cezanneZheng Bao2021-03-221-0/+1
* soc/amd/cezanne/Kconfig: turn on GOPNikolai Vyssotski2021-03-141-0/+2
* soc/amd/cezanne: Add USB ports to chipset.cbMathew King2021-03-101-0/+2
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