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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-08 22:57:31 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-17 16:24:16 +0000 |
| commit | d5ab24cd48006022ca60fe35f0f0366f3edce748 (patch) | |
| tree | 914c025a4c2ae34645a07033f5403089e213d9eb /src/soc/amd/cezanne/Kconfig | |
| parent | 75547dbc53cde54dc83e26ef22828ce7cf9e2ba2 (diff) | |
| download | coreboot-d5ab24cd48006022ca60fe35f0f0366f3edce748.tar.gz coreboot-d5ab24cd48006022ca60fe35f0f0366f3edce748.tar.bz2 coreboot-d5ab24cd48006022ca60fe35f0f0366f3edce748.zip | |
soc/amd/common/acpi/cppc: add nominal and minimum frequencies
Now that we have functionality to get the minimal and nominal
frequencies, the corresponding fields in the CPPC config can now be
populated. If the HOB isn't present and/or the frequency values
could not be obtained, CPPC_UNSUPPORTED is still used; otherwise the
HOB-provided frequency in MHz is used for those two fields.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Id3257690a3388d44ceceb7ac4f1db3d49e195caa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66551
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index d40c37c75701..ce1688941aba 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -68,6 +68,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SSE2 |