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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 22:10:05 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-12 21:52:12 +0000 |
| commit | 8f7f4bf87a238dd046a376804b9e53162092f601 (patch) | |
| tree | 2c31aa38216a8fa376c8203a5435eda08138704f /src/soc/amd/cezanne/Kconfig | |
| parent | 6cf0e4a3536750cb1cd9ecec56463731db647fe5 (diff) | |
| download | coreboot-8f7f4bf87a238dd046a376804b9e53162092f601.tar.gz coreboot-8f7f4bf87a238dd046a376804b9e53162092f601.tar.bz2 coreboot-8f7f4bf87a238dd046a376804b9e53162092f601.zip | |
soc/amd/cezanne,common: factor out CPPC code to common AMD SoC code
The Cezanne CPPC ACPI table generation code also applies to Sabrina, so
move it to the common AMD SoC code directory so that it can be used for
Sabrina too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 91129e921d73..d40c37c75701 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -39,6 +39,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS select SOC_AMD_COMMON_BLOCK_AOAC |