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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 23:37:58 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:52 +0000 |
| commit | 62afdb675a49bfebbdd4f186f696c15a56d64348 (patch) | |
| tree | 50fa03f35315cb3e6e13c3960bd1b6d5c0aae288 /src/soc/amd/cezanne/Makefile.inc | |
| parent | 45b6080561748fe579c8ee901811cf4043383c2f (diff) | |
| download | coreboot-62afdb675a49bfebbdd4f186f696c15a56d64348.tar.gz coreboot-62afdb675a49bfebbdd4f186f696c15a56d64348.tar.bz2 coreboot-62afdb675a49bfebbdd4f186f696c15a56d64348.zip | |
soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses
some of the registers directly.
BUG=b:183149183
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 050ba44be98c..5fda4b0b826d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -10,6 +10,7 @@ all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += reset.c |