soc/amd/common: Add func to clear eSPI IO & memory decode ranges

Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges.  This clears all the ranges so
the eSPI configuration can start fresh.

BUG=b:183207262, b:183974365
TEST=Verify on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index c593e02d49e9..7ca5b05e3234 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -107,6 +107,13 @@ int espi_open_mmio_window(uint32_t base, size_t size);
 void espi_configure_decodes(void);
 
 /*
+ * Clear all configured eSPI memory and I/O decode ranges.  This is useful for changing
+ * the decodes, or if something else has previously setup decode windows that conflict
+ * with the windows that coreboot needs.
+ */
+void espi_clear_decodes(void);
+
+/*
  * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
  * SPIBASE. This is required for cases where verstage runs on PSP.
  */