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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-05 13:57:30 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-13 17:37:39 +0000 |
| commit | 2d17ea4d501c8e0f68813cda80dd6412b10ca0d8 (patch) | |
| tree | d58219f9780325c10a5b8ae02c56e1235f2995b4 /src/soc/amd/common/block/include/amdblocks/espi.h | |
| parent | 425e73d3f545430884ad2020d56300aae88a1714 (diff) | |
| download | coreboot-2d17ea4d501c8e0f68813cda80dd6412b10ca0d8.tar.gz coreboot-2d17ea4d501c8e0f68813cda80dd6412b10ca0d8.tar.bz2 coreboot-2d17ea4d501c8e0f68813cda80dd6412b10ca0d8.zip | |
soc/amd/common/block/espi_util: Refactor eSPI Setup
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks/espi.h')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/espi.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 9a563f9e36ea..7e49ea0f2e5f 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -131,4 +131,15 @@ int espi_setup(void); /* Run mainboard configuration needed to set up eSPI */ void mb_set_up_early_espi(void); +/* Setup eSPI with any mainboard specific initialization. */ +static inline void configure_espi(void) +{ + /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform + port80h routing as early as possible. */ + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + mb_set_up_early_espi(); + espi_setup(); + } +} + #endif /* AMD_BLOCK_ESPI_H */ |