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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-30 15:40:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-01 11:39:01 +0000 |
| commit | dde265f5a22c7b75a2d502a66ae706e6b1e04561 (patch) | |
| tree | 2a9a1ff5441cd998376649fefa03e67cc64d9c27 /src/soc/amd/mendocino/early_fch.c | |
| parent | fbda323e8af2b0556abb0c76beca4482c58af8a2 (diff) | |
| download | coreboot-dde265f5a22c7b75a2d502a66ae706e6b1e04561.tar.gz coreboot-dde265f5a22c7b75a2d502a66ae706e6b1e04561.tar.bz2 coreboot-dde265f5a22c7b75a2d502a66ae706e6b1e04561.zip | |
soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the
legacy PCI config space access is needed on all AMD SoCs, implement a
common add_pci_cfg_resources function that reports both and gets called
from amd_pci_domain_read_resources and don't report those in the SoC-
specific code any more. The only functional change is that on Genoa now
the IO ports used for the legacy PCI config space access get reserved.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/mendocino/early_fch.c')
0 files changed, 0 insertions, 0 deletions