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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-05 13:57:30 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-13 17:37:39 +0000 |
| commit | 2d17ea4d501c8e0f68813cda80dd6412b10ca0d8 (patch) | |
| tree | d58219f9780325c10a5b8ae02c56e1235f2995b4 /src/soc/amd/picasso/early_fch.c | |
| parent | 425e73d3f545430884ad2020d56300aae88a1714 (diff) | |
| download | coreboot-2d17ea4d501c8e0f68813cda80dd6412b10ca0d8.tar.gz coreboot-2d17ea4d501c8e0f68813cda80dd6412b10ca0d8.tar.bz2 coreboot-2d17ea4d501c8e0f68813cda80dd6412b10ca0d8.zip | |
soc/amd/common/block/espi_util: Refactor eSPI Setup
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/early_fch.c')
| -rw-r--r-- | src/soc/amd/picasso/early_fch.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 3d1cd1b2e7c8..8771e387bc79 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -45,7 +45,10 @@ void fch_pre_init(void) /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access the GPIO registers. */ enable_acpimmio_decode_pm04(); + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); + /* Setup eSPI to enable port80 routing. */ + configure_espi(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); @@ -81,7 +84,4 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - espi_setup(); } |