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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-13 20:07:26 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-14 18:45:39 +0000 |
| commit | 43cd1c0bbedd852a9d5e53a32c75826e8bdcc8b2 (patch) | |
| tree | e3e8e3d4e37c9605be286f8db3f9ba1bd6c5b336 /src/soc/amd/picasso/include/soc/southbridge.h | |
| parent | 151cc6c14bd758ea6f9691f79792d33adce60698 (diff) | |
| download | coreboot-43cd1c0bbedd852a9d5e53a32c75826e8bdcc8b2.tar.gz coreboot-43cd1c0bbedd852a9d5e53a32c75826e8bdcc8b2.tar.bz2 coreboot-43cd1c0bbedd852a9d5e53a32c75826e8bdcc8b2.zip | |
soc/amd/common/block/pm: rework pm_set_power_failure_state
Picasso and Stoneyridge didn't do a read-modify-write operation on the
lower nibble of PM_RTC_SHADOW_REG, but just wrote the upper nibble as
all zeros. Since the upper nibble might be uninitialized before the
lower nibble gets written, do what Picasso and Stoneyridge did here
instead of what the reference code does. Also add a comment why and how
this register behaves a bit weird.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bda2349e3ae84cba50b187cc773fd8a5b17f4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/include/soc/southbridge.h')
0 files changed, 0 insertions, 0 deletions