diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-01-22 09:53:18 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-23 20:14:34 +0000 |
| commit | b5e27a81cc971af3c7e5e4c8038d23593339b66c (patch) | |
| tree | ebeded253bc40eab82481d0fc4b3d0a57e592e01 /src/soc/amd/picasso/pcie_gpp.c | |
| parent | 91839eef5cb47ec82e9b9d824ac49d7edbff0534 (diff) | |
| download | coreboot-b5e27a81cc971af3c7e5e4c8038d23593339b66c.tar.gz coreboot-b5e27a81cc971af3c7e5e4c8038d23593339b66c.tar.bz2 coreboot-b5e27a81cc971af3c7e5e4c8038d23593339b66c.zip | |
soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array
I think it makes the code a bit cleaner.
BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/pcie_gpp.c')
| -rw-r--r-- | src/soc/amd/picasso/pcie_gpp.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 1acd021c9cd7..722dc88f9029 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -21,20 +21,20 @@ struct pci_routing { unsigned int devfn; unsigned int group; - const char intx[5]; + uint8_t pin[4]; }; /* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ static const struct pci_routing pci_routing_table[] = { - {PCIE_GPP_0_DEVFN, 0, "ABCD"}, - {PCIE_GPP_1_DEVFN, 1, "ABCD"}, - {PCIE_GPP_2_DEVFN, 2, "ABCD"}, - {PCIE_GPP_3_DEVFN, 3, "ABCD"}, - {PCIE_GPP_4_DEVFN, 4, "ABCD"}, - {PCIE_GPP_5_DEVFN, 5, "ABCD"}, - {PCIE_GPP_6_DEVFN, 6, "ABCD"}, - {PCIE_GPP_A_DEVFN, 7, "ABCD"}, - {PCIE_GPP_B_DEVFN, 7, "CDAB"}, + {PCIE_GPP_0_DEVFN, 0, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_1_DEVFN, 1, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_2_DEVFN, 2, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_3_DEVFN, 3, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_4_DEVFN, 4, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_5_DEVFN, 5, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_6_DEVFN, 6, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_A_DEVFN, 7, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_B_DEVFN, 7, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, }; /* @@ -71,7 +71,7 @@ static unsigned int calculate_irq(const struct pci_routing *pci_routing, unsigne { unsigned int irq_index; irq_index = pci_routing->group * 4; - irq_index += pci_routing->intx[i] - 'A'; + irq_index += pci_routing->pin[i]; return irq_index; } |